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* ice40: reduce ABC9 internal fanout warnings with a param for CI->I3Eddie Hung2020-01-246-32/+26
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* Merge pull request #1652 from YosysHQ/eddie/abc9_fixesEddie Hung2020-01-221-4/+6
|\ | | | | Eddie/abc9 fixes
| * abc9: error out if flip-flop init is 1'b1 for '-dff'Eddie Hung2020-01-221-0/+2
| | | | | | | | Due to ABC sequential synthesis restriction
| * abc9: fix scratchpad entry abc9.verifyEddie Hung2020-01-221-4/+4
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* Merge pull request #1637 from YosysHQ/mwk/fix-1634Claire Wolf2020-01-211-9/+17
|\ | | | | fsm_detect: Add a cache to avoid excessive CPU usage for big mux networks.
| * fsm_detect: Add a cache to avoid excessive CPU usage for big mux networks.Marcin Kościelnicki2020-01-141-9/+17
| | | | | | | | Fixes #1634.
* | Merge pull request #1629 from YosysHQ/mwk/edif-zClaire Wolf2020-01-211-0/+2
|\ \ | | | | | | edif: Just ignore connections to 'z
| * | edif: Just ignore connections to 'zMarcin Kościelnicki2020-01-131-0/+2
| | | | | | | | | | | | | | | Connecting a const 'z to a net should be equivalent to not connecting it at all, so let's just ignore such connections on output.
* | | Merge pull request #1621 from YosysHQ/clifford/fminitClaire Wolf2020-01-202-0/+198
|\ \ \ | | | | | | | | Add fminit pass
| * | | Add fminit passClifford Wolf2020-01-092-0/+198
| | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | | Merge pull request #1643 from YosysHQ/eddie/cleanup_arith_mapEddie Hung2020-01-182-125/+88
|\ \ \ \ | | | | | | | | | | Cleanup +/xilinx/arith_map.v
| * | | | Deprecate `_CLB_CARRY from +/xilinx/arith_map.v since #1623Eddie Hung2020-01-172-119/+82
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| * | | | +/xilinx/arith_map.v fix $lcu ruleEddie Hung2020-01-171-6/+6
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* | | | | Merge pull request #1602 from niklasnisbeth/ice40-init-vals-warningDavid Shah2020-01-181-2/+8
|\ \ \ \ \ | | | | | | | | | | | | ice40: Demote conflicting FF init values to a warning
| * | | | | ice40: Demote conflicting FF init values to a warningNiklas Nisbeth2019-12-311-2/+8
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* | | | | | Merge pull request #1645 from YosysHQ/eddie/fix1644Eddie Hung2020-01-179-20/+52
|\ \ \ \ \ \ | |_|/ / / / |/| | | | | {ice40,xilinx}_dsp: improve robustess
| * | | | | xilinx_dsp: another typo; move xilinx specific testEddie Hung2020-01-172-1/+1
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| * | | | | ice40_dsp: fix typoEddie Hung2020-01-172-2/+13
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| * | | | | ConsistencyEddie Hung2020-01-172-4/+6
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| * | | | | xilinx_dsp: add parameter defaultsEddie Hung2020-01-171-7/+7
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| * | | | | Add #1644 testcaseEddie Hung2020-01-172-0/+2
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| * | | | | synth_ice40: call wreduce before mul2dspEddie Hung2020-01-171-1/+2
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| * | | | | ice40_dsp: add testEddie Hung2020-01-171-0/+11
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| * | | | | ice40_dsp: add default values for parametersEddie Hung2020-01-172-11/+11
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| * | | | | ice40_dsp: tolerant of fanout-less outputs, as well as all-zero inputsEddie Hung2020-01-171-0/+5
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* | | | | Merge pull request #1639 from YosysHQ/eddie/fix_read_xaigerEddie Hung2020-01-152-2/+14
|\ \ \ \ \ | | | | | | | | | | | | read_aiger: $lut prefix in front
| * | | | | abc9: aAdd test to check $_NOT_s are absorbedEddie Hung2020-01-151-0/+12
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| * | | | | read_aiger: $lut prefix in frontEddie Hung2020-01-151-2/+2
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* | | | | | Merge pull request #1636 from YosysHQ/eddie/fix_synth_xilinx_WMiodrag Milanović2020-01-151-1/+1
|\ \ \ \ \ \ | |/ / / / / |/| | | | | synth_xilinx: fix default W value for non-xc7
| * | | | | synth_xilinx: fix default W value for non-xc7Eddie Hung2020-01-141-1/+1
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* | | | | | Merge pull request #1635 from YosysHQ/eddie/print_statsEddie Hung2020-01-141-25/+13
|\ \ \ \ \ \ | |_|_|_|_|/ |/| | | | | print_stats footer to return peak memory, option for including children
| * | | | | As before, only display MEM if Linux or FreeBSDEddie Hung2020-01-141-3/+7
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| * | | | | print_stats footer to return peak memory, option for including childrenEddie Hung2020-01-141-28/+12
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* | | | | Merge pull request #1633 from YosysHQ/eddie/fix_autonameEddie Hung2020-01-142-1/+20
|\ \ \ \ \ | | | | | | | | | | | | autoname: do not rename ports
| * | | | | autoname: do not autoname portsEddie Hung2020-01-141-1/+1
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| * | | | | autoname: add testcase with $-prefix-ed portEddie Hung2020-01-141-0/+19
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* | | | | Merge pull request #1632 from YosysHQ/eddie/fix1630Eddie Hung2020-01-145-17/+23
|\ \ \ \ \ | | | | | | | | | | | | read_aiger: uniquify wires with $aiger<autoidx> prefix
| * | | | | read_aiger: also rename "$0"Eddie Hung2020-01-141-2/+2
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| * | | | | read_aiger: uniquify wires with $aiger<autoidx> prefixEddie Hung2020-01-132-9/+13
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| * | | | | Add #1630 testcaseEddie Hung2020-01-132-0/+2
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| * | | | | read_aiger: make $and/$not/$lut the prefix not suffixEddie Hung2020-01-132-9/+9
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* | | | | Merge pull request #1623 from YosysHQ/mmicko/edif_attrMiodrag Milanović2020-01-145-35/+46
|\ \ \ \ \ | |/ / / / |/| | | | Export wire properties in EDIF
| * | | | this one is fineMiodrag Milanovic2020-01-101-3/+3
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| * | | | Fix testsMiodrag Milanovic2020-01-103-12/+11
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| * | | | remove whitespaceMiodrag Milanovic2020-01-101-1/+1
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| * | | | Use CARRY4 for abc1 as well, preventing issues with VivadoMiodrag Milanovic2020-01-101-1/+1
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| * | | | Export wire properties as well in EDIFMiodrag Milanovic2020-01-101-26/+38
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* | | | | Merge pull request #1620 from YosysHQ/eddie/abc9_scratchpadEddie Hung2020-01-136-36/+147
|\ \ \ \ \ | | | | | | | | | | | | abc9: add some scripts/options into "scratchpad"
| * | | | | Another conflictEddie Hung2020-01-111-1/+0
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| * | | | | MIssed this merge conflictEddie Hung2020-01-111-4/+0
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