| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | [wip] DSP48E1 sim model improvements | David Shah | 2019-08-06 | 1 | -23/+120 |
| | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
| * | [wip] DSP48E1 sim model improvements | David Shah | 2019-08-06 | 1 | -8/+75 |
| | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
| * | Add comment about supporting $dffe in ice40_dsp | Eddie Hung | 2019-08-01 | 1 | -0/+1 |
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| * | Pack P register properly | Eddie Hung | 2019-08-01 | 1 | -2/+4 |
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| * | Trim Y_WIDTH | Eddie Hung | 2019-08-01 | 1 | -5/+3 |
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| * | Add DSP_SIGNEDONLY back | Eddie Hung | 2019-08-01 | 1 | -0/+16 |
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| * | DSP_MINWIDTH -> DSP_{A,B,Y}_MINWIDTH | Eddie Hung | 2019-08-01 | 2 | -5/+12 |
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| * | Change $__softmul back to $mul | Eddie Hung | 2019-08-01 | 1 | -0/+1 |
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| * | Cope with sign extension in mul2dsp | Eddie Hung | 2019-08-01 | 2 | -14/+14 |
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| * | Revert "Do not do sign extension in techmap; let packer do it" | Eddie Hung | 2019-08-01 | 1 | -5/+14 |
| | | | | | This reverts commit 595a8f032f1e9db385959f92a4a414a40de291fd. | ||||
| * | Merge remote-tracking branch 'origin/master' into xc7dsp | Eddie Hung | 2019-08-01 | 25 | -86/+219 |
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| | * | Merge pull request #1236 from YosysHQ/eddie/xc6s_brams_map | Eddie Hung | 2019-08-01 | 1 | -3/+3 |
| | |\ | | | | | | | xc6s_brams_map.v: RST -> RSTBRST for RAMB8BWER | ||||
| | | * | RST -> RSTBRST for RAMB8BWER | Eddie Hung | 2019-07-29 | 1 | -3/+3 |
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| | * | | Merge pull request #1233 from YosysHQ/clifford/defer | Clifford Wolf | 2019-07-31 | 2 | -49/+21 |
| | |\ \ | | |/ | |/| | Call "read_verilog" with -defer from "read" | ||||
| | | * | Update README to use "read" instead of "read_verilog" | Clifford Wolf | 2019-07-29 | 1 | -48/+19 |
| | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| | | * | Call "read_verilog" with -defer from "read" | Clifford Wolf | 2019-07-29 | 1 | -1/+2 |
| | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| | * | | Merge pull request #1228 from YosysHQ/dave/yy_buf_size | Eddie Hung | 2019-07-29 | 1 | -0/+3 |
| | |\ \ | | | | | | | | | verilog_lexer: Increase YY_BUF_SIZE to 65536 | ||||
| | | * | | verilog_lexer: Increase YY_BUF_SIZE to 65536 | David Shah | 2019-07-26 | 1 | -0/+3 |
| | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
| | * | | | Merge pull request #1234 from mmicko/fix_gzip_no_exist | David Shah | 2019-07-29 | 1 | -19/+21 |
| | |\ \ \ | | |_|/ | |/| | | Fix case when file does not exist | ||||
| | | * | | Fix case when file does not exist | Miodrag Milanovic | 2019-07-29 | 1 | -19/+21 |
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| | * | | Merge pull request #1226 from YosysHQ/dave/gzip | David Shah | 2019-07-27 | 8 | -13/+70 |
| | |\ \ | | |/ | |/| | Add support for gzip'd input files | ||||
| | | * | Update CHANGELOG | David Shah | 2019-07-26 | 1 | -1/+1 |
| | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
| | | * | Fix frontend auto-detection for gzipped input | David Shah | 2019-07-26 | 1 | -9/+12 |
| | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
| | | * | Add support for reading gzip'd input files | David Shah | 2019-07-26 | 6 | -3/+57 |
| | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
| | * | | Merge branch 'master' of github.com:YosysHQ/yosys | Eddie Hung | 2019-07-25 | 17 | -29/+360 |
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| | | * \ | Merge branch 'ZirconiumX-synth_intel_m9k' | Clifford Wolf | 2019-07-25 | 4 | -5/+11 |
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| | | | * | | intel: Map M9K BRAM only on families that have it | Dan Ravensloft | 2019-07-23 | 4 | -5/+12 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This regresses Cyclone V and Cyclone 10 substantially, but these numbers were artificial, targeting a BRAM that they did not contain. Amusingly, synth_intel still does better when synthesizing PicoSoC than Quartus when neither are inferring block RAM. | ||||
| | | * | | | Merge pull request #1218 from ZirconiumX/synth_intel_iopads | Clifford Wolf | 2019-07-25 | 1 | -8/+8 |
| | | |\ \ \ | | | | | | | | | | | | | intel: Make -noiopads the default | ||||
| | | | * | | | intel: Make -noiopads the default | Dan Ravensloft | 2019-07-24 | 1 | -8/+8 |
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| | | * | | | | Merge pull request #1219 from jakobwenzel/objIterator | Clifford Wolf | 2019-07-25 | 2 | -3/+20 |
| | | |\ \ \ \ | | | | | | | | | | | | | | | made ObjectIterator comply with Iterator Interface | ||||
| | | | * | | | | replaced std::iterator with using statements | Jakob Wenzel | 2019-07-25 | 1 | -6/+6 |
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| | | | * | | | | made ObjectIterator extend std::iterator | Jakob Wenzel | 2019-07-24 | 2 | -2/+19 |
| | | | |/ / / | | | | | | | | | | | | | | | | | | | this makes it possible to use std algorithms on them | ||||
| | | * | | | | Merge pull request #1224 from YosysHQ/xilinx_fix_ff | Eddie Hung | 2019-07-25 | 1 | -2/+2 |
| | | |\ \ \ \ | | | |_|_|/ | | |/| | | | xilinx: Fix missing cell name underscore in cells_map.v | ||||
| | | | * | | | xilinx: Fix missing cell name underscore in cells_map.v | David Shah | 2019-07-25 | 1 | -2/+2 |
| | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
| | | * | | | | Merge pull request #1222 from koriakin/s6-example | Eddie Hung | 2019-07-24 | 5 | -0/+47 |
| | | |\ \ \ \ | | | |_|/ / | | |/| | | | Add a simple example for Spartan 6 | ||||
| | | | * | | | Add a simple example for Spartan 6 | Marcin Kościelnicki | 2019-07-24 | 5 | -0/+47 |
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| | | * | | | Merge pull request #1212 from YosysHQ/eddie/signed_ice40_dsp | Eddie Hung | 2019-07-23 | 3 | -9/+241 |
| | | |\ \ \ | | | | | | | | | | | | | ice40: Fix SB_MAC16 sim model for signed modes | ||||
| | | * \ \ \ | Merge pull request #1214 from jakobwenzel/astmod_clone | Eddie Hung | 2019-07-22 | 1 | -0/+2 |
| | | |\ \ \ \ | | | |_|_|/ | | |/| | | | initialize noblackbox and nowb in AstModule::clone | ||||
| | | | * | | | initialize noblackbox and nowb in AstModule::clone | Jakob Wenzel | 2019-07-22 | 1 | -0/+2 |
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| | | * | | | Add "stat -tech cmos" | Clifford Wolf | 2019-07-20 | 1 | -2/+29 |
| | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| | * | | | | Bump abc to fix &mfs bug | Eddie Hung | 2019-07-25 | 1 | -1/+1 |
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| * | | | | Fix B_WIDTH > DSP_B_MAXWIDTH case | Eddie Hung | 2019-08-01 | 1 | -32/+14 |
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| * | | | | CO is sign extension only if signed multiplier | Eddie Hung | 2019-08-01 | 1 | -1/+6 |
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| * | | | | Fix typo | Eddie Hung | 2019-08-01 | 1 | -1/+1 |
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| * | | | | Do not compute sign bit if result is zero | Eddie Hung | 2019-07-31 | 1 | -1/+2 |
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| * | | | | For signed multipliers, compute sign bit separately... | Eddie Hung | 2019-07-31 | 1 | -23/+42 |
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| * | | | | Restore old CO behaviour | Eddie Hung | 2019-07-31 | 1 | -6/+7 |
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| * | | | | Helper: SigSpec::operator[] to accept negative indices | Eddie Hung | 2019-07-31 | 1 | -2/+2 |
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| * | | | | Fix spacing | Eddie Hung | 2019-07-26 | 1 | -3/+3 |
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| * | | | | Update test_autotb doc to reflect default value of zero | Eddie Hung | 2019-07-26 | 1 | -1/+3 |
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index : iCE40/yosys | |
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