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* DSP48E1 sim model: fix seq tests and add preadder testsDavid Shah2019-08-082-6/+91
| | | | Signed-off-by: David Shah <dave@ds0.me>
* DSP48E1 sim model: seq test workingDavid Shah2019-08-083-16/+60
| | | | Signed-off-by: David Shah <dave@ds0.me>
* DSP48E1 sim model: Comb, no pre-adder, mode workingDavid Shah2019-08-082-8/+13
| | | | Signed-off-by: David Shah <dave@ds0.me>
* [wip] sim model testingDavid Shah2019-08-084-15/+77
| | | | Signed-off-by: David Shah <dave@ds0.me>
* [wip] sim model testingDavid Shah2019-08-083-40/+360
| | | | Signed-off-by: David Shah <dave@ds0.me>
* [wip] DSP48E1 sim model improvementsDavid Shah2019-08-071-6/+82
| | | | Signed-off-by: David Shah <dave@ds0.me>
* [wip] DSP48E1 sim model improvementsDavid Shah2019-08-061-23/+120
| | | | Signed-off-by: David Shah <dave@ds0.me>
* [wip] DSP48E1 sim model improvementsDavid Shah2019-08-061-8/+75
| | | | Signed-off-by: David Shah <dave@ds0.me>
* Add comment about supporting $dffe in ice40_dspEddie Hung2019-08-011-0/+1
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* Pack P register properlyEddie Hung2019-08-011-2/+4
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* Trim Y_WIDTHEddie Hung2019-08-011-5/+3
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* Add DSP_SIGNEDONLY backEddie Hung2019-08-011-0/+16
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* DSP_MINWIDTH -> DSP_{A,B,Y}_MINWIDTHEddie Hung2019-08-012-5/+12
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* Change $__softmul back to $mulEddie Hung2019-08-011-0/+1
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* Cope with sign extension in mul2dspEddie Hung2019-08-012-14/+14
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* Revert "Do not do sign extension in techmap; let packer do it"Eddie Hung2019-08-011-5/+14
| | | | This reverts commit 595a8f032f1e9db385959f92a4a414a40de291fd.
* Merge remote-tracking branch 'origin/master' into xc7dspEddie Hung2019-08-0125-86/+219
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| * Merge pull request #1236 from YosysHQ/eddie/xc6s_brams_mapEddie Hung2019-08-011-3/+3
| |\ | | | | | | xc6s_brams_map.v: RST -> RSTBRST for RAMB8BWER
| | * RST -> RSTBRST for RAMB8BWEREddie Hung2019-07-291-3/+3
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| * | Merge pull request #1233 from YosysHQ/clifford/deferClifford Wolf2019-07-312-49/+21
| |\ \ | | |/ | |/| Call "read_verilog" with -defer from "read"
| | * Update README to use "read" instead of "read_verilog"Clifford Wolf2019-07-291-48/+19
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| | * Call "read_verilog" with -defer from "read"Clifford Wolf2019-07-291-1/+2
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Merge pull request #1228 from YosysHQ/dave/yy_buf_sizeEddie Hung2019-07-291-0/+3
| |\ \ | | | | | | | | verilog_lexer: Increase YY_BUF_SIZE to 65536
| | * | verilog_lexer: Increase YY_BUF_SIZE to 65536David Shah2019-07-261-0/+3
| | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * | | Merge pull request #1234 from mmicko/fix_gzip_no_existDavid Shah2019-07-291-19/+21
| |\ \ \ | | |_|/ | |/| | Fix case when file does not exist
| | * | Fix case when file does not existMiodrag Milanovic2019-07-291-19/+21
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| * | Merge pull request #1226 from YosysHQ/dave/gzipDavid Shah2019-07-278-13/+70
| |\ \ | | |/ | |/| Add support for gzip'd input files
| | * Update CHANGELOGDavid Shah2019-07-261-1/+1
| | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| | * Fix frontend auto-detection for gzipped inputDavid Shah2019-07-261-9/+12
| | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| | * Add support for reading gzip'd input filesDavid Shah2019-07-266-3/+57
| | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * | Merge branch 'master' of github.com:YosysHQ/yosysEddie Hung2019-07-2517-29/+360
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| | * \ Merge branch 'ZirconiumX-synth_intel_m9k'Clifford Wolf2019-07-254-5/+11
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| | | * | intel: Map M9K BRAM only on families that have itDan Ravensloft2019-07-234-5/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This regresses Cyclone V and Cyclone 10 substantially, but these numbers were artificial, targeting a BRAM that they did not contain. Amusingly, synth_intel still does better when synthesizing PicoSoC than Quartus when neither are inferring block RAM.
| | * | | Merge pull request #1218 from ZirconiumX/synth_intel_iopadsClifford Wolf2019-07-251-8/+8
| | |\ \ \ | | | | | | | | | | | | intel: Make -noiopads the default
| | | * | | intel: Make -noiopads the defaultDan Ravensloft2019-07-241-8/+8
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| | * | | | Merge pull request #1219 from jakobwenzel/objIteratorClifford Wolf2019-07-252-3/+20
| | |\ \ \ \ | | | | | | | | | | | | | | made ObjectIterator comply with Iterator Interface
| | | * | | | replaced std::iterator with using statementsJakob Wenzel2019-07-251-6/+6
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| | | * | | | made ObjectIterator extend std::iteratorJakob Wenzel2019-07-242-2/+19
| | | |/ / / | | | | | | | | | | | | | | | | | | this makes it possible to use std algorithms on them
| | * | | | Merge pull request #1224 from YosysHQ/xilinx_fix_ffEddie Hung2019-07-251-2/+2
| | |\ \ \ \ | | | |_|_|/ | | |/| | | xilinx: Fix missing cell name underscore in cells_map.v
| | | * | | xilinx: Fix missing cell name underscore in cells_map.vDavid Shah2019-07-251-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| | * | | | Merge pull request #1222 from koriakin/s6-exampleEddie Hung2019-07-245-0/+47
| | |\ \ \ \ | | | |_|/ / | | |/| | | Add a simple example for Spartan 6
| | | * | | Add a simple example for Spartan 6Marcin Kościelnicki2019-07-245-0/+47
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| | * | | Merge pull request #1212 from YosysHQ/eddie/signed_ice40_dspEddie Hung2019-07-233-9/+241
| | |\ \ \ | | | | | | | | | | | | ice40: Fix SB_MAC16 sim model for signed modes
| | * \ \ \ Merge pull request #1214 from jakobwenzel/astmod_cloneEddie Hung2019-07-221-0/+2
| | |\ \ \ \ | | | |_|_|/ | | |/| | | initialize noblackbox and nowb in AstModule::clone
| | | * | | initialize noblackbox and nowb in AstModule::cloneJakob Wenzel2019-07-221-0/+2
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| | * | | Add "stat -tech cmos"Clifford Wolf2019-07-201-2/+29
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | | Bump abc to fix &mfs bugEddie Hung2019-07-251-1/+1
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* | | | Fix B_WIDTH > DSP_B_MAXWIDTH caseEddie Hung2019-08-011-32/+14
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* | | | CO is sign extension only if signed multiplierEddie Hung2019-08-011-1/+6
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* | | | Fix typoEddie Hung2019-08-011-1/+1
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