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* abc9_ops: -prep_dff_map to warn if no specify cellsEddie Hung2020-05-141-7/+12
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* ice40: synth_ice40 cleanupEddie Hung2020-05-141-13/+3
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* ecp5: replace ecp5_ffinit with techmap rules + dff2dffs -match-initEddie Hung2020-05-143-64/+220
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* kernel: Module::makeblackbox() to clear connections + delete wires lastEddie Hung2020-05-141-0/+1
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* ice40: add synth_ice40 -dff option, support with -abc9Eddie Hung2020-05-142-8/+41
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* ice40: split out cells_map.v into ff_map.vEddie Hung2020-05-143-31/+29
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* abc9_ops: -prep_dff_map to cope with plain $_DFF_[NP]_ flopsEddie Hung2020-05-141-12/+39
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* synth_xilinx: rename dff_mode -> dffEddie Hung2020-05-141-8/+10
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* xaiger: do not treat (* init=1'bx *) as 1'b0Eddie Hung2020-05-141-1/+1
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* abc9: cleanupEddie Hung2020-05-141-4/+1
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* abc9_ops: do not use (* abc9_init *)Eddie Hung2020-05-141-16/+31
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* aiger: -xaiger to parse initial state back into (* init *) on Q wireEddie Hung2020-05-141-1/+2
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* xaiger: when -dff use (* init *) for initial stateEddie Hung2020-05-141-3/+15
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* abc9_ops: add 'dff' label for auto handling of (* abc9_flop *) boxesEddie Hung2020-05-149-635/+398
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* abc9: fix behaviour and help for -box optionEddie Hung2020-05-141-3/+7
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* aiger: -xaiger to read $_DFF_[NP]_ back with new clocks createdEddie Hung2020-05-142-3/+24
| | | | according to mergeability class, and init state as cell attr
* xaiger: output $_DFF_[NP]_ with mergeability if -dff optionEddie Hung2020-05-141-42/+44
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* Merge pull request #2045 from YosysHQ/eddie/fix2042Eddie Hung2020-05-146-1/+107
|\ | | | | verilog: error if no direction given for task arguments, default to input in SV mode
| * test: add another testcase as per @nakengelhardtEddie Hung2020-05-141-0/+25
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| * verilog: default to input in sv mode if task/func has no dir ...Eddie Hung2020-05-131-2/+10
| | | | | | | | otherwise error
| * tests: update/extend task argument testsEddie Hung2020-05-132-2/+35
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| * verilog: error out when non-ANSI task/func argumentsEddie Hung2020-05-111-1/+5
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| * tests: add #2042 testcaseEddie Hung2020-05-111-0/+12
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| * Setup tests/verilog properlyEddie Hung2020-05-113-0/+24
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* | Merge pull request #2052 from YosysHQ/claire/verific_memfixClaire Wolf2020-05-141-2/+12
|\ \ | | | | | | Add support for non-power-of-two mem chunks in verific importer
| * | Add support for non-power-of-two mem chunks in verific importerClaire Wolf2020-05-141-2/+12
| | | | | | | | | | | | Signed-off-by: Claire Wolf <claire@symbioticeda.com>
* | | Merge pull request #2050 from YosysHQ/eddie/opt_clean_fixesClaire Wolf2020-05-142-12/+32
|\ \ \ | | | | | | | | opt_clean: remove (* init *) regardless of -purge, remove (* init *) when consistent with sigmap, clean to behave identically
| * | | opt_clean: improve warning messageEddie Hung2020-05-142-2/+2
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| * | | opt_clean: add init testEddie Hung2020-05-141-0/+13
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| * | | opt_clean: rminit without -purge; also remove if consistent with const..Eddie Hung2020-05-141-9/+17
| | | | | | | | | | | | | | | | warn otherwise
| * | | opt_clean: really make 'clean' identical to 'opt_clean' by rminit tooEddie Hung2020-05-141-3/+2
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* | | Merge pull request #2027 from YosysHQ/eddie/verilog_neg_uptoClaire Wolf2020-05-144-8/+35
|\ \ \ | |/ / |/| | ast: swap range regardless of range_left >= 0
| * | techlibs/common: more robustness when *_WIDTH = 0Eddie Hung2020-05-053-8/+30
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| * | ast: swap range regardless of range_left >= 0Eddie Hung2020-05-041-1/+1
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| * | test: add failing testEddie Hung2020-05-041-0/+5
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* | | ice40: fix ICESTORM_LC process sensitivityEddie Hung2020-05-121-1/+1
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* | | ice40: fix whitespaceEddie Hung2020-05-121-15/+14
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* | | ecp5: Add missing SERDES parametersDavid Shah2020-05-121-0/+4
| |/ |/| | | | | Signed-off-by: David Shah <dave@ds0.me>
* | Merge pull request #2038 from nakengelhardt/no-libdir-flagClaire Wolf2020-05-081-2/+1
|\ \ | | | | | | Remove yosys libdir from LDFLAGS (and fix a typo)
| * | Remove yosys libdir from LDFLAGS (and fix a typo)N. Engelhardt2020-05-071-2/+1
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* | | Fix clang compiler warningClaire Wolf2020-05-081-2/+2
| | | | | | | | | | | | Signed-off-by: Claire Wolf <claire@symbioticeda.com>
* | | Merge pull request #2022 from Xiretza/fallthroughswhitequark2020-05-085-9/+26
|\ \ \ | | | | | | | | Avoid switch fall-through warnings
| * | | Reorder cases to avoid fall-through warningXiretza2020-05-071-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | log_assert(false) never returns and thus can't fall through, but gcc doesn't seem to think that far. Making it the last case avoids the problem entirely.
| * | | Add YS_FALLTHROUGH macro to mark case fall-throughXiretza2020-05-075-6/+23
| | | | | | | | | | | | | | | | | | | | C++17 introduced [[fallthrough]], GCC and clang had their own vendored attributes before that. MSVC doesn't seem to have such a warning at all.
* | | | intel_alm: direct LUTRAM cell instantiationDan Ravensloft2020-05-079-52/+163
| |/ / |/| | | | | | | | | | | | | | | | | | | | | | | | | | By instantiating the LUTRAM cell directly, we avoid a trip through altsyncram, which speeds up Quartus synthesis time. This also gives a little more flexibility, as Yosys can build RAMs out of individual 32x1 LUTRAM cells. While working on this, I discovered that the mem_init0 parameter of <family>_mlab_cell gets ignored by Quartus.
* | | Merge pull request #2005 from YosysHQ/claire/fix1990Claire Wolf2020-05-079-19/+142
|\ \ \ | | | | | | | | Add "nowrshmsk" attribute, fix shift-and-mask bit slice write for signed offset
| * | | Fix the other "opt_expr -fine" bug introduced in 213a89558Claire Wolf2020-05-021-7/+19
| | | | | | | | | | | | | | | | Signed-off-by: Claire Wolf <claire@symbioticeda.com>
| * | | Add plusargs for output files in test_autotb outputClaire Wolf2020-05-021-3/+10
| | | | | | | | | | | | | | | | Signed-off-by: Claire Wolf <claire@symbioticeda.com>
| * | | Bugfix in partsel.v signed indices test casesClaire Wolf2020-05-021-2/+2
| | | | | | | | | | | | | | | | Signed-off-by: Claire Wolf <claire@symbioticeda.com>
| * | | Fix handling of signed indices in bit slicesClaire Wolf2020-05-021-3/+8
| | | | | | | | | | | | | | | | Signed-off-by: Claire Wolf <claire@symbioticeda.com>
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