| Commit message (Collapse) | Author | Age | Files | Lines | ||
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| | | * | | | | | | synth_ice40: switch -relut to be always on. | whitequark | 2019-07-11 | 1 | -10/+4 | |
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| | | * | | | | | | synth_ice40: fix help text typo. NFC. | whitequark | 2019-07-11 | 1 | -1/+1 | |
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| | * | | | | | | Merge pull request #1182 from koriakin/xc6s-bram | Eddie Hung | 2019-07-11 | 9 | -8/+598 | |
| | |\ \ \ \ \ \ | | | | | | | | | | | | | | | | | synth_xilinx: Initial Spartan 6 block RAM inference support. | |||||
| | | * | | | | | | synth_xilinx: Initial Spartan 6 block RAM inference support. | Marcin Kościelnicki | 2019-07-11 | 9 | -8/+598 | |
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| | * | | | | | | Merge pull request #1185 from koriakin/xc-ff-init-vals | Eddie Hung | 2019-07-11 | 2 | -6/+6 | |
| | |\ \ \ \ \ \ | | | | | | | | | | | | | | | | | xilinx: Fix the default values for FDPE/FDSE INIT attributes to match ISE/Vivado. | |||||
| | | * | | | | | | xilinx: Fix the default values for FDPE/FDSE INIT attributes to match ↵ | Marcin Kościelnicki | 2019-07-11 | 2 | -6/+6 | |
| | | |/ / / / / | | | | | | | | | | | | | | | | | | | | | | ISE/Vivado. | |||||
| | * / / / / / | Enable &mfs for abc9, even if it only currently works for ice40 | Eddie Hung | 2019-07-11 | 1 | -1/+1 | |
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| | * | | | | | Merge pull request #1172 from whitequark/write_verilog-Sa-as-qmark | Clifford Wolf | 2019-07-11 | 1 | -2/+8 | |
| | |\ \ \ \ \ | | | | | | | | | | | | | | | write_verilog: write RTLIL::Sa aka - as Verilog ? | |||||
| | | * | | | | | write_verilog: write RTLIL::Sa aka - as Verilog ?. | whitequark | 2019-07-09 | 1 | -2/+8 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, the only ways (determined by grepping for regex \bSa\b) to end up with RTLIL::Sa in a netlist is by reading a Verilog constant with ? in it as a part of case, or by running certain FSM passes. Both of these cases should be round-tripped back to ? in Verilog. | |||||
| | * | | | | | | Merge pull request #1179 from whitequark/attrmap-proc | Clifford Wolf | 2019-07-11 | 1 | -0/+19 | |
| | |\ \ \ \ \ \ | | | | | | | | | | | | | | | | | attrmap: also consider process, switch and case attributes | |||||
| | | * | | | | | | attrmap: also consider process, switch and case attributes. | whitequark | 2019-07-10 | 1 | -0/+19 | |
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| * | | | | | | | Add Tsu offset to boxes, and comments | Eddie Hung | 2019-07-11 | 1 | -6/+11 | |
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| * | | | | | | | ABC doesn't like negative delays in flop boxes... | Eddie Hung | 2019-07-11 | 1 | -6/+6 | |
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| * | | | | | | | Fix FDCE_1 box | Eddie Hung | 2019-07-11 | 1 | -1/+1 | |
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| * | | | | | | | Revert "$pastQ should be first input" | Eddie Hung | 2019-07-11 | 1 | -13/+13 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 8f9d529929f43e6ba98f06159ae9533984c6264f. | |||||
| * | | | | | | | Propagate INIT attr | Eddie Hung | 2019-07-11 | 1 | -5/+5 | |
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| * | | | | | | | $pastQ should be first input | Eddie Hung | 2019-07-11 | 1 | -13/+13 | |
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| * | | | | | | | Fix typo | Eddie Hung | 2019-07-11 | 1 | -1/+1 | |
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| * | | | | | | | Short out async box | Eddie Hung | 2019-07-11 | 1 | -0/+14 | |
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| * | | | | | | | Simplify to $__ABC_ASYNC box | Eddie Hung | 2019-07-11 | 2 | -19/+8 | |
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| * | | | | | | | $__ABC_FD_ASYNC_MUX.Q -> Y | Eddie Hung | 2019-07-11 | 1 | -1/+1 | |
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| * | | | | | | | Missing debug message | Eddie Hung | 2019-07-11 | 1 | -0/+1 | |
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| * | | | | | | | Error out if abc9 not called with -lut or -luts | Eddie Hung | 2019-07-11 | 1 | -0/+3 | |
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| * | | | | | | | Count $_NOT_ cells turned into $luts | Eddie Hung | 2019-07-11 | 1 | -7/+2 | |
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| * | | | | | | | WIP for fixing partitioning, temporarily do not partition | Eddie Hung | 2019-07-11 | 1 | -12/+34 | |
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| * | | | | | | | Restore from master | Eddie Hung | 2019-07-10 | 1 | -0/+1 | |
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| * | | | | | | | Another typo | Eddie Hung | 2019-07-10 | 1 | -1/+1 | |
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| * | | | | | | | abc_flop to also get topologically sorted | Eddie Hung | 2019-07-10 | 1 | -11/+10 | |
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| * | | | | | | | write_verilog with *.v extension | Eddie Hung | 2019-07-10 | 1 | -1/+1 | |
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| * | | | | | | | Fix clk_pol for FD*_1 | Eddie Hung | 2019-07-10 | 2 | -4/+3 | |
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| * | | | | | | | Another typo | Eddie Hung | 2019-07-10 | 1 | -1/+1 | |
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| * | | | | | | | Another typo | Eddie Hung | 2019-07-10 | 1 | -1/+1 | |
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| * | | | | | | | Fix spacing | Eddie Hung | 2019-07-10 | 1 | -1/+1 | |
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| * | | | | | | | Use \$currQ | Eddie Hung | 2019-07-10 | 1 | -4/+9 | |
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| * | | | | | | | Remove -retime from abc9, revert to abc behav with separate clock/en domains | Eddie Hung | 2019-07-10 | 1 | -29/+61 | |
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| * | | | | | | | Preserve all parameters, plus some extra ones for clk/en polarity | Eddie Hung | 2019-07-10 | 1 | -10/+66 | |
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| * | | | | | | | Small opt | Eddie Hung | 2019-07-10 | 1 | -2/+1 | |
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| * | | | | | | | Change how to specify flops to ABC again | Eddie Hung | 2019-07-10 | 3 | -33/+63 | |
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| * | | | | | | | Use split_tokens() | Eddie Hung | 2019-07-10 | 2 | -25/+19 | |
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| * | | | | | | | Remove params from FD*_1 variants | Eddie Hung | 2019-07-10 | 1 | -12/+3 | |
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| * | | | | | | | Fix typo, and have !{PRE,CLR} behave as CE | Eddie Hung | 2019-07-10 | 1 | -14/+14 | |
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| * | | | | | | | Move ABC FF stuff to abc_ff.v; add support for other FD* types | Eddie Hung | 2019-07-10 | 4 | -27/+135 | |
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| * | | | | | | | Uncomment IS_C_INVERTED parameter | Eddie Hung | 2019-07-10 | 1 | -1/+1 | |
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| * | | | | | | | synth_xilinx's map_cells stage to techmap ff_map.v | Eddie Hung | 2019-07-10 | 1 | -0/+2 | |
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| * | | | | | | | Fix box numbering | Eddie Hung | 2019-07-10 | 2 | -5/+5 | |
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| * | | | | | | | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-07-10 | 39 | -246/+999 | |
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| | * | | | | | | Merge pull request #1180 from YosysHQ/eddie/no_abc9_retime | Eddie Hung | 2019-07-10 | 3 | -6/+15 | |
| | |\ \ \ \ \ \ | | | | | | | | | | | | | | | | | Error out if -abc9 and -retime specified | |||||
| | | * | | | | | | Error out if -abc9 and -retime specified | Eddie Hung | 2019-07-10 | 3 | -6/+15 | |
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| | * | | | | | | Merge pull request #1148 from YosysHQ/xc7mux | Eddie Hung | 2019-07-10 | 7 | -49/+415 | |
| | |\ \ \ \ \ \ | | | | | | | | | | | | | | | | | synth_xilinx to infer wide multiplexers using new '-widemux <min>' option | |||||
| | | * | | | | | | Add some spacing | Eddie Hung | 2019-07-10 | 1 | -9/+9 | |
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index : iCE40/yosys | |
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