aboutsummaryrefslogtreecommitdiffstats
Commit message (Collapse)AuthorAgeFilesLines
* wild guessing at the problem because it builds fine on my machinesN. Engelhardt2020-10-161-0/+3
|
* sim -vcd: add date, version, and option for timescaleN. Engelhardt2020-10-161-0/+17
|
* Bump versionYosys Bot2020-10-161-1/+1
|
* Merge pull request #2398 from jakobwenzel/smtbmc-escapeclairexen2020-10-151-11/+29
|\ | | | | smtbmc: escape identifiers in verilog testbench
| * smtbmc: escape identifiers in verilog testbenchJakob Wenzel2020-10-061-11/+29
| |
* | Bump versionYosys Bot2020-10-131-1/+1
| |
* | extend verific library API for formal apps and generatorsMiodrag Milanovic2020-10-121-15/+83
| |
* | Bump versionYosys Bot2020-10-091-1/+1
| |
* | opt_clean: Better memory handling.Marcelina Kościelnicka2020-10-082-8/+94
|/ | | | | | | | Previously, `$memwr` and `$meminit` cells were always preserved (along with the memory itself). With this change, they are instead part of the main cell mark-and-sweep pass: a memory (and its `$meminit` and `$memwr` cells) is only preserved iff any associated `$memrd` cell needs to be preserved.
* Bump versionYosys Bot2020-10-061-1/+1
|
* Update required Verific versionMiodrag Milanović2020-10-051-1/+1
|
* Bump versionYosys Bot2020-10-031-1/+1
|
* Merge pull request #2396 from YosysHQ/claire/empty-paramclairexen2020-10-021-0/+3
|\ | | | | Ignore empty parameters in Verilog module instantiations
| * Ignore empty parameters in Verilog module instantiationsClaire Xenia Wolf2020-10-011-0/+3
| | | | | | | | | | | | Fixes #2394 Signed-off-by: Claire Xenia Wolf <claire@symbioticeda.com>
* | Bump versionYosys Bot2020-10-021-1/+1
|/
* Merge pull request #2378 from udif/pr_dollar_high_lowclairexen2020-10-014-31/+159
|\ | | | | Added $high(), $low(), $left(), $right()
| * We can now handle array slices (e.g. $size(x[1]) etc. )Udi Finkelstein2020-09-172-9/+20
| |
| * Fixed comments, removed debug messageUdi Finkelstein2020-09-161-5/+5
| |
| * Added $high(), $low(), $left(), $right()Udi Finkelstein2020-09-154-30/+147
| |
* | Merge pull request #2380 from Xiretza/parallel-testsclairexen2020-10-0121-230/+156
|\ \ | | | | | | Clean up and parallelize testsuite
| * | tests: add gitignores for auto-generated makefilesXiretza2020-09-262-0/+2
| | |
| * | tests/simple: remove "nullglob" shoptXiretza2020-09-211-1/+0
| | |
| * | tests: ParallelizeXiretza2020-09-213-9/+20
| | |
| * | tests: Centralize test collection and Makefile generationXiretza2020-09-2116-222/+136
| | |
* | | Update .gitignoreDavid Shah2020-10-011-0/+2
| | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | Merge pull request #2395 from YosysHQ/sha1_if_contain_spacesclairexen2020-10-011-2/+18
|\ \ \ | | | | | | | | Use sha1 for parameter list in case if they contain spaces
| * | | use sha1 for parameter list in case if they contain spacesMiodrag Milanovic2020-09-301-2/+18
| | | |
* | | | Bump versionYosys Bot2020-10-011-1/+1
|/ / /
* | | Fixed installation dir override for Python scriptsMiodrag Milanovic2020-09-301-6/+6
| | |
* | | Bump versionYosys Bot2020-09-301-1/+1
| | |
* | | Merge pull request #2393 from nakengelhardt/no_const_sensitivityclairexen2020-09-293-7/+102
|\ \ \ | | | | | | | | write_verilog: emit intermediate wire for constant values in sensitivity list
| * | | add testsN. Engelhardt2020-09-282-0/+49
| | | |
| * | | write_verilog: emit intermediate wire for constant values in sensitivity listN. Engelhardt2020-09-281-7/+53
| | | |
* | | | Merge pull request #2392 from YosysHQ/mmicko/hierarchy_fixclairexen2020-09-291-5/+7
|\ \ \ \ | | | | | | | | | | Validate parameters only when they are used
| * | | | Validate parameters only when they are usedMiodrag Milanovic2020-09-251-5/+7
| | | | |
* | | | | Bump versionYosys Bot2020-09-291-1/+1
| |/ / / |/| | |
* | | | Merge pull request #2386 from btut/fix/pyinstallpathMiodrag Milanović2020-09-281-2/+1
|\ \ \ \ | | | | | | | | | | Fixed python installation path
| * | | | Fixed python installation pathBenedikt Tutzer2020-09-251-2/+1
| |/ / / | | | | | | | | | | | | | | | | | | | | The path where python expects it's libraries seems to change from operating system to operating system, but can be querried from the site package.
* | | | Merge pull request #2387 from btut/fix/pythonWrappersCXXFlagsN. Engelhardt2020-09-281-1/+1
|\ \ \ \ | |/ / / |/| | | Use CXXFLAGS to enable pyosys specific code before generating wrappers
| * | | Use CXXFLAGS to enable pyosys specific code before generating wrappersBenedikt Tutzer2020-09-251-1/+1
|/ / / | | | | | | | | | | | | | | | The .pyh files were generated without the CXXFLAGS. This meant that code marked by the WITH_PYTHON flag was excluded. This is fixed by adding the flag in the rule for .pyh files.
* | | Bump versionYosys Bot2020-09-241-1/+1
| | |
* | | xilinx: do not make DSP48E1 a whitebox for ABC9 by default (#2325)Eddie Hung2020-09-233-17/+102
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * xilinx: eliminate SCCs from DSP48E1 model * xilinx: add SCC test for DSP48E1 * Update techlibs/xilinx/cells_sim.v * xilinx: Gate DSP48E1 being a whitebox behind ALLOW_WHITEBOX_DSP48E1 Have a test that checks it works through ABC9 when enabled
* | | Merge pull request #2384 from nakengelhardt/fix_2383Miodrag Milanović2020-09-231-1/+1
|\ \ \ | | | | | | | | switch argument order to work with macOS getopt
| * | | switch argument order to work with macOS getoptN. Engelhardt2020-09-231-1/+1
|/ / /
* | | Bump versionYosys Bot2020-09-221-1/+1
| | |
* | | Merge pull request #2372 from nakengelhardt/name_is_publicN. Engelhardt2020-09-2114-25/+27
|\ \ \ | |/ / |/| | add IdString::isPublic()
| * | use the new isPublic() in a few placesN. Engelhardt2020-09-1413-25/+25
| | |
| * | add IdString::isPublic()N. Engelhardt2020-09-031-0/+2
| | |
* | | Bump versionYosys Bot2020-09-191-1/+1
| | |
* | | Merge pull request #2381 from YosysHQ/unsupportedclairexen2020-09-181-2/+8
|\ \ \ | | | | | | | | Better error for unsupported SVA sequence
generated by cgit v1.2.3 (git 2.25.1) at 2025-02-25 15:07:27 +0000