| Commit message (Collapse) | Author | Age | Files | Lines | ||
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| * | | sv: improve support for wire and var with user-defined types | Brett Witherspoon | 2021-08-12 | 3 | -11/+152 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - User-defined types must be data types. Using a net type (e.g. wire) is a syntax error. - User-defined types without a net type are always variables (i.e. logic). - Nets and variables can now be explicitly declared using user-defined types: typedef logic [1:0] W; wire W w; typedef logic [1:0] V; var V v; Fixes #2846 | |||||
| * | | Bump version | github-actions[bot] | 2021-08-13 | 1 | -1/+1 | |
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| * | | memory_share: Pass addresses through sigmap_xmux everywhere. | Marcelina Kościelnicka | 2021-08-13 | 1 | -20/+25 | |
| |/ | | | | This fixes wide port recognition in some cases. | |||||
| * | Bump version | github-actions[bot] | 2021-08-12 | 1 | -1/+1 | |
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| * | test/arch/{ecp5,ice40}/memories.ys: Use read_verilog -defer. | Marcelina Kościelnicka | 2021-08-11 | 2 | -78/+156 | |
| | | | | | | | | | | | These parts keep rereading a Verilog module, then using chparam to test it with various parameter combinations. Since the default parameters are on the large side, this spends a lot of time needlessly elaborating the default parametrization that will then be discarded. Fix it with -deref and manual hierarchy call. Shaves 30s off the test time on my machine. | |||||
| * | memory_dff: Recognize read ports with reset / initial value. | Marcelina Kościelnicka | 2021-08-11 | 4 | -8/+55 | |
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| * | proc_memwr: Use the v2 memwr cell. | Marcelina Kościelnicka | 2021-08-11 | 3 | -14/+24 | |
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| * | Add v2 memory cells. | Marcelina Kościelnicka | 2021-08-11 | 22 | -206/+631 | |
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| * | Bump version | github-actions[bot] | 2021-08-11 | 1 | -1/+1 | |
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| * | kernel/mem: Introduce transparency masks. | Marcelina Kościelnicka | 2021-08-11 | 8 | -118/+408 | |
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| * | Allow optional comma after last entry in enum | Michael Singer | 2021-08-09 | 1 | -11/+12 | |
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| * | Bump version | github-actions[bot] | 2021-08-10 | 1 | -1/+1 | |
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| * | Refactor common parts of SAT-using optimizations into a helper. | Marcelina Kościelnicka | 2021-08-09 | 7 | -153/+224 | |
| | | | | | | | | | | | | | | This also aligns the functionality: - in all cases, the onehot attribute is used to create appropriate constraints (previously, opt_dff didn't do it at all, and share created one-hot constraints based on $pmux presence alone, which is unsound) - in all cases, shift and mul/div/pow cells are now skipped when importing the SAT problem (previously only memory_share did this) — this avoids creating clauses for hard cells that are unlikely to help with proving the UNSATness needed for optimization | |||||
| * | Bump version | github-actions[bot] | 2021-08-08 | 1 | -1/+1 | |
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| * | opt_merge: Use FfInitVals. | Marcelina Kościelnicka | 2021-08-08 | 3 | -28/+51 | |
| | | | | | Partial #2920 fix. | |||||
| * | Bump version | github-actions[bot] | 2021-08-07 | 1 | -1/+1 | |
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| * | verilog: Support tri/triand/trior wire types. | Marcelina Kościelnicka | 2021-08-06 | 1 | -0/+3 | |
| | | | | | | | These are, by the standard, just aliases for wire/wand/wor. Fixes #2918. | |||||
| * | Bump version | github-actions[bot] | 2021-08-05 | 1 | -1/+1 | |
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| * | memory_share: Don't skip ports with EN wired to input for SAT sharing. | Marcelina Kościelnicka | 2021-08-04 | 1 | -3/+1 | |
| | | | | | Fixes #2912. | |||||
| * | Bump version | github-actions[bot] | 2021-08-04 | 1 | -1/+1 | |
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| * | memory_bram: Move init data swizzling before other swizzling. | Marcelina Kościelnicka | 2021-08-03 | 1 | -18/+18 | |
| | | | | | Fixes #2907. | |||||
| * | Bump version | github-actions[bot] | 2021-08-03 | 1 | -1/+1 | |
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| * | Require latest verific | Miodrag Milanovic | 2021-08-02 | 1 | -1/+1 | |
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| * | Bump version | github-actions[bot] | 2021-08-02 | 1 | -1/+1 | |
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| * | backend/verilog: Add alternate mode for transparent read port output. | Marcelina Kościelnicka | 2021-08-01 | 1 | -1/+71 | |
| | | | | | | | This mode will be used whenever read port cannot be handled in the "extract address register" way, ie. whenever it has enable, reset, init functionality or (in the future) mixed transparency mask. | |||||
| * | memory_bram: Some refactoring | Marcelina Kościelnicka | 2021-08-01 | 1 | -196/+174 | |
| | | | | | | | This will make more sense when the new transparency masks land. Fixes #2902. | |||||
| * | Bump version | github-actions[bot] | 2021-07-31 | 1 | -1/+1 | |
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| * | Update version.yml | Miodrag Milanović | 2021-07-30 | 1 | -2/+5 | |
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| * | Fixes xc7 BRAM36s | Maciej Dudek | 2021-07-30 | 1 | -4/+6 | |
| | | | | | | | UG473 from Xilinx states that 15 bit should always be set if RAMB isn't in cascade mode. Signed-off-by: Maciej Dudek <mdudek@antmicro.com> | |||||
| * | proc_rmdead: use explicit pattern set when there are no wildcards | Zachary Snow | 2021-07-29 | 4 | -2/+386 | |
| | | | | | | | | | If width of a case expression was large, explicit patterns could cause the existing logic to take an extremely long time, or exhaust the maximum size of the underlying set. For cases where all of the patterns are fully defined and there are no constants in the case expression, this change uses a simple set to track which patterns have been seen. | |||||
| * | genrtlil: add width detection for AST_PREFIX nodes | Zachary Snow | 2021-07-29 | 2 | -0/+26 | |
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| * | Bump version | github-actions[bot] | 2021-07-30 | 1 | -1/+1 | |
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| * | opt_lut: Allow more than one -dlogic per cell type. | Marcelina Kościelnicka | 2021-07-29 | 3 | -24/+55 | |
| | | | | | Fixes #2061. | |||||
| * | verilog: save and restore overwritten macro arguments | Zachary Snow | 2021-07-28 | 4 | -4/+54 | |
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| * | Bump version | github-actions[bot] | 2021-07-29 | 1 | -1/+1 | |
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| * | verilog: Emit $meminit_v2 cell. | Marcelina Kościelnicka | 2021-07-28 | 5 | -55/+87 | |
| | | | | | Fixes #2447. | |||||
| * | backends/verilog: Support meminit with mask. | Marcelina Kościelnicka | 2021-07-28 | 1 | -3/+18 | |
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| * | memory: Introduce $meminit_v2 cell, with EN input. | Marcelina Kościelnicka | 2021-07-28 | 10 | -13/+86 | |
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| * | Bump version | github-actions[bot] | 2021-07-28 | 1 | -1/+1 | |
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| * | proc: Run opt_expr at the end | Marcelina Kościelnicka | 2021-07-27 | 1 | -0/+11 | |
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| * | opt_expr: Propagate constants to port connections. | Marcelina Kościelnicka | 2021-07-27 | 3 | -3/+37 | |
| | | | | | | | | | This adds one simple piece of functionality to opt_expr: when a cell port is connected to a fully-constant signal (as determined by sigmap), the port is reconnected directly to the constant value. This is just enough optimization to fix the "non-constant $meminit input" problem without requiring a full opt_clean or a separate pass. | |||||
| * | Bump version | github-actions[bot] | 2021-07-27 | 1 | -1/+1 | |
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| * | Add version bump workflow | Miodrag Milanovic | 2021-07-26 | 1 | -0/+31 | |
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| * | Update to latest verific | Miodrag Milanovic | 2021-07-21 | 1 | -3/+3 | |
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| * | Use new read_id_num helper function elsewhere in hierarchy.cc | Rupert Swarbrick | 2021-07-20 | 1 | -5/+6 | |
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| * | Extract connection checking logic from expand_module in hierarchy.cc | Rupert Swarbrick | 2021-07-20 | 1 | -23/+64 | |
| | | | | | | No functional change, but pulls more logic out of the expand_module function. | |||||
| * | Merge pull request #2885 from whitequark/cxxrtl-fix-2883 | whitequark | 2021-07-20 | 1 | -2/+8 | |
| |\ | | | | | cxxrtl: treat wires with multiple defs as not inlinable | |||||
| | * | cxxrtl: treat wires with multiple defs as not inlinable. | whitequark | 2021-07-20 | 1 | -2/+8 | |
| | | | | | | | | | Fixes #2883. | |||||
| * | | Merge pull request #2884 from whitequark/cxxrtl-fix-2882 | whitequark | 2021-07-20 | 1 | -10/+12 | |
| |\ \ | |/ |/| | cxxrtl: treat assignable internal wires used only for debug as locals | |||||
| | * | cxxrtl: treat assignable internal wires used only for debug as locals. | whitequark | 2021-07-20 | 1 | -10/+12 | |
| |/ | | | | | | This issue was introduced in commit 4aa65f40 while fixing #2739. Fixes #2882. | |||||
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