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* | Improve igloo2 exampleClifford Wolf2019-01-084-5/+29
|/ | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fix typo in manualClifford Wolf2019-01-071-1/+1
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Bugfix in $memrd sharingClifford Wolf2019-01-071-2/+6
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Merge pull request #782 from whitequark/flowmap_dfsClifford Wolf2019-01-073-124/+243
|\ | | | | flowmap: construct a max-volume max-flow min-cut, not just any one
| * flowmap: construct a max-volume max-flow min-cut, not just any one.whitequark2019-01-061-7/+10
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| * flowmap: add -minlut option, to allow postprocessing with opt_lut.whitequark2019-01-041-7/+21
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| * flowmap: cleanup for clarity. NFCI.whitequark2019-01-043-107/+179
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| * flowmap: improve debug graph output. NFC.whitequark2019-01-041-47/+76
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| * flowmap: add link to longer version of paper. NFC.whitequark2019-01-041-2/+3
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* | Switch "bugpoint" from system() to run_command()Clifford Wolf2019-01-071-1/+1
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Merge pull request #783 from whitequark/bugpointClifford Wolf2019-01-072-1/+370
|\ \ | | | | | | bugpoint: new pass
| * | bugpoint: new pass.whitequark2019-01-072-1/+370
|/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A typical use of `bugpoint` would involve a script with a pass under test, e.g.: flowmap -relax -optarea 100 and would be invoked as: bugpoint -yosys ./yosys -script flowmap.ys -clean -cells This replaces the current design with the minimal design that still crashes the `flowmap.ys` script. `bugpoint` can also be used to perform generic design minimization using `select`, e.g. the following script: select i:* %x t:$_MUX_ %i -assert-max 0 would remove all parts of the design except for an unbroken path from an input to an output port that goes through exactly one $_MUX_ cell. (The condition is inverted.)
* | Merge pull request #780 from phire/rename_from_wireClifford Wolf2019-01-061-0/+66
|\ \ | | | | | | Rename cells based on the wires they drive.
| * | Rename cells based on the wires they drive.Scott Mansell2019-01-061-0/+66
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* | | Add skeleton Yosys-Libero igloo2 example projectClifford Wolf2019-01-055-0/+44
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | Bugfix in Verilog string handlingClifford Wolf2019-01-051-1/+1
|/ / | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Merge pull request #777 from mmicko/achronix_cell_sim_fixClifford Wolf2019-01-041-1/+1
|\ \ | | | | | | Fix cells_sim.v for Achronix FPGA
| * | Fix cells_sim.v for Achronix FPGAMiodrag Milanovic2019-01-041-1/+1
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* | Remove -m32 Verific eval lib build instructionsClifford Wolf2019-01-041-29/+0
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Merge pull request #776 from mmicko/unify_noflattenClifford Wolf2019-01-044-8/+16
|\ \ | | | | | | Unify usage of noflatten among architectures
| * | Unify usage of noflatten among architecturesMiodrag Milanovic2019-01-044-8/+16
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* / Update Verific default pathClifford Wolf2019-01-041-1/+1
|/ | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Merge pull request #775 from whitequark/opt_flowmapClifford Wolf2019-01-033-1/+875
|\ | | | | flowmap: new techmap pass
| * flowmap: new techmap pass.whitequark2019-01-033-1/+875
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* | Merge pull request #770 from whitequark/opt_expr_cmpClifford Wolf2019-01-023-97/+178
|\ \ | |/ |/| opt_expr: refactor and improve simplification of comparisons
| * opt_expr: improve simplification of comparisons with large constants.whitequark2019-01-022-70/+65
| | | | | | | | | | | | | | | | | | | | | | | | The idea behind this simplification is that a N-bit signal X being compared with an M-bit constant where M>N and the constant has Nth or higher bit set, it either always succeeds or always fails. However, the existing implementation only worked with one-hot signals for some reason. It also printed incorrect messages. This commit adjusts the simplification to have as much power as possible, and fixes other bugs.
| * opt_expr: refactor simplification of unsigned X<onehot and X>=onehot. NFCI.whitequark2019-01-022-31/+42
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| * opt_expr: refactor simplification of signed X>=0 and X<0. NFCI.whitequark2019-01-022-32/+40
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| * opt_expr: simplify any unsigned comparisons with all-0 and all-1.whitequark2019-01-023-17/+84
| | | | | | | | | | | | Before this commit, only unsigned comparisons with all-0 would be simplified. This commit also makes the code handling such comparisons to be more rigorous and not abort on unexpected input.
* | Merge pull request #755 from Icenowy/anlogic-dram-initClifford Wolf2019-01-026-2/+96
|\ \ | | | | | | anlogic: implement DRAM initialization
| * | anlogic: implement DRAM initializationIcenowy Zheng2018-12-206-2/+96
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As the TD tool doesn't accept the DRAM cell to contain unknown values in the initial value, the initialzation support of DRAM is previously skipped. Now add the support by add a new pass to determine unknown values in the initial value. Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
* | | Merge branch 'master' of github.com:YosysHQ/yosysClifford Wolf2019-01-0211-35/+256
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| * \ \ Merge pull request #750 from Icenowy/anlogic-ff-initClifford Wolf2019-01-023-17/+45
| |\ \ \ | | | | | | | | | | Initialization of Anlogic DFFs
| | * | | anlogic: set the init value of DFFsIcenowy Zheng2018-12-182-14/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As dffinit has already supported for different initialization strings for DFFs and check for re-initialization, initialization of Anlogic DFFs are now ready to go. Support for set the init values of Anlogic DFFs. Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
| | * | | Add "dffinit -noreinit" parameterIcenowy Zheng2018-12-181-1/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Sometimes the FF cell might be initialized during the map process, e.g. some FPGA platforms (Anlogic Eagle and Lattice ECP5 for example) has only a "SR" pin for a FF for async reset, that resets the FF to the initial value, which means the async reset value should be set as the initial value. In this case the DFFINIT pass shouldn't reinitialize it to a different value, which will lead to error. Add a "-noreinit" parameter for the safeguard. If a FF is not technically initialized before DFFINIT pass, the default value should be set to x. Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
| | * | | Add "dffinit -strinit high low"Icenowy Zheng2018-12-181-2/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On some platforms the string to initialize DFF might not be "high" and "low", e.g. with Anlogic TD it's "SET" and "RESET". Add a "-strinit" parameter for dffinit to allow specify the strings used for high and low. Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
| * | | | Merge pull request #773 from whitequark/opt_lut_elim_fixesClifford Wolf2019-01-021-8/+31
| |\ \ \ \ | | | | | | | | | | | | opt_lut: elimination fixes
| | * | | | opt_lut: reflect changes in sigmap.whitequark2019-01-021-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | Otherwise, some LUTs will be missed during elimination.
| | * | | | opt_lut: use a worklist, and revisit cells affected by elimination.whitequark2019-01-021-3/+10
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| | * | | | opt_lut: count eliminated cells, and set opt.did_something for them.whitequark2019-01-021-6/+20
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| * | | | Merge pull request #772 from whitequark/synth_lutClifford Wolf2019-01-022-7/+41
| |\ \ \ \ | | | | | | | | | | | | synth: add k-LUT mode
| | * | | | synth_ice40: use 4-LUT coarse synthesis mode.whitequark2019-01-021-1/+1
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| | * | | | synth: add k-LUT mode.whitequark2019-01-021-2/+36
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| | * | | | synth: improve script documentation. NFC.whitequark2019-01-021-6/+6
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| * | | | | Merge pull request #771 from whitequark/techmap_cmp2lutClifford Wolf2019-01-025-3/+139
| |\| | | | | | | | | | | | | | | | cmp2lut: new techmap pass
| | * | | | cmp2lut: new techmap pass.whitequark2019-01-025-3/+139
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* | / / / Improve VerificImporter support for writes to asymmetric memoriesClifford Wolf2019-01-021-22/+35
|/ / / / | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | | Fix VerificImporter asymmetric memories error messageClifford Wolf2019-01-021-1/+1
| | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | | Merge pull request #769 from whitequark/typosClifford Wolf2019-01-0240-74/+74
|\ \ \ \ | |/ / / |/| | | Fix typographical and grammatical errors and inconsistencies
| * | | Fix typographical and grammatical errors and inconsistencies.whitequark2019-01-0240-74/+74
|/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The initial list of hits was generated with the codespell command below, and each hit was evaluated and fixed manually while taking context into consideration. DIRS="kernel/ frontends/ backends/ passes/ techlibs/" DIRS="${DIRS} libs/ezsat/ libs/subcircuit" codespell $DIRS -S *.o -L upto,iff,thru,synopsys,uint More hits were found by looking through comments and strings manually.
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-07 16:11:10 +0000