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* Made changes recommended by Clifford Wolf ...luke whittlesey2015-05-101-22/+11
| | | | | | Removed bit_check_equal(), used RTLIL::SigBit for individual bits, used dict<> instead of std::map, and used RTLIL::SigSpec instead of std::vector.
* Verilog backend for $mem cells should now be able to handle differentluke whittlesey2015-05-081-50/+105
| | | | write-enable bits and RD_TRANSPARENT parameter settings.
* Added support for $mem cells in the verilog backend.luke whittlesey2015-05-071-1/+120
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* Minor fixes in handling of "init" attributeClifford Wolf2015-04-091-7/+7
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* Added "init" attribute support to verilog backendClifford Wolf2015-04-041-0/+5
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* Added Verilog backend $dffsr supportClifford Wolf2015-03-181-1/+51
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* Fixed "write_verilog -attr2comment" handling of "*/" in stringsClifford Wolf2015-02-131-2/+4
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* Added dict/pool.sort()Clifford Wolf2015-01-241-0/+2
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* Cosmetic changes in verilog output formatClifford Wolf2015-01-021-5/+10
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* Replaced std::unordered_map as implementation for Yosys::dictClifford Wolf2014-12-261-25/+25
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* Added Yosys::{dict,nodict,vector} container typesClifford Wolf2014-12-261-1/+1
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* Added $dffe support to write_verilogClifford Wolf2014-12-201-3/+14
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* Fixed generation of temp names in verilog backendClifford Wolf2014-11-071-4/+5
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* Renamed SIZE() to GetSize() because of name collision on Win32Clifford Wolf2014-10-101-1/+1
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* namespace YosysClifford Wolf2014-09-271-4/+3
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* Various bug fixes (related to $macc model testing)Clifford Wolf2014-09-061-1/+2
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* Removed $bu0 cell typeClifford Wolf2014-09-041-1/+0
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* Using $pos models for $bu0Clifford Wolf2014-09-031-16/+1
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* Changed backend-api from FILE to std::ostreamClifford Wolf2014-08-231-230/+230
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* Fixed AOI/OAI expr handling in verilog backendClifford Wolf2014-08-161-4/+4
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* Added additional gate types: $_NAND_ $_NOR_ $_XNOR_ $_AOI3_ $_OAI3_ $_AOI4_ ↵Clifford Wolf2014-08-161-4/+40
| | | | $_OAI4_
* Renamed $_INV_ cell type to $_NOT_Clifford Wolf2014-08-151-1/+1
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* Refactoring of CellType classClifford Wolf2014-08-141-10/+28
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* Be more conservative with printing decimal numbers in verilog backendClifford Wolf2014-08-021-2/+3
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* Improved verilog output for ordinary $mux cellsClifford Wolf2014-08-021-3/+19
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* More cleanups related to RTLIL::IdString usageClifford Wolf2014-08-021-6/+6
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* Renamed port access function on RTLIL::Cell, added param access functionsClifford Wolf2014-07-311-40/+40
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* Added support for "upto" wires to Verilog front- and back-endClifford Wolf2014-07-281-9/+22
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* Using log_assert() instead of assert()Clifford Wolf2014-07-281-3/+2
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* Refactoring: Renamed RTLIL::Design::modules to modules_Clifford Wolf2014-07-271-1/+1
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* Refactoring: Renamed RTLIL::Module::cells to cells_Clifford Wolf2014-07-271-3/+3
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* Refactoring: Renamed RTLIL::Module::wires to wires_Clifford Wolf2014-07-271-4/+4
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* Added RTLIL::Cell::has(portname)Clifford Wolf2014-07-261-2/+2
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* Manual fixes for new cell connections APIClifford Wolf2014-07-261-4/+4
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* Changed users of cell->connections_ to the new API (sed command)Clifford Wolf2014-07-261-43/+43
| | | | | | | | | git grep -l 'connections_' | xargs sed -i -r -e ' s/(->|\.)connections_\["([^"]*)"\] = (.*);/\1set("\2", \3);/g; s/(->|\.)connections_\["([^"]*)"\]/\1get("\2")/g; s/(->|\.)connections_.at\("([^"]*)"\)/\1get("\2")/g; s/(->|\.)connections_.push_back/\1connect/g; s/(->|\.)connections_/\1connections()/g;'
* Renamed RTLIL::{Module,Cell}::connections to connections_Clifford Wolf2014-07-261-43/+43
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* Various RTLIL::SigSpec related code cleanupsClifford Wolf2014-07-251-21/+29
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* Removed RTLIL::SigSpec::optimize()Clifford Wolf2014-07-231-3/+0
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* SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, ↵Clifford Wolf2014-07-221-2/+2
| | | | created interim RTLIL::SigSpec::chunks_rw()
* SigSpec refactoring: using the accessor functions everywhereClifford Wolf2014-07-221-29/+29
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* SigSpec refactoring: renamed chunks and width to __chunks and __widthClifford Wolf2014-07-221-29/+29
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* Use functions instead of always blocks for $mux/$pmux/$safe_pmux in verilog ↵Clifford Wolf2014-07-201-17/+21
| | | | backend
* Added support for $bu0 to verilog backendClifford Wolf2014-07-201-0/+16
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* Added $slice and $concat cell typesClifford Wolf2014-02-071-0/+22
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* Added support for non-const === and !== (for miter circuits)Clifford Wolf2013-12-271-6/+8
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* Replaced signed_parameters API with CONST_FLAG_SIGNEDClifford Wolf2013-12-041-1/+1
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* Replaced RTLIL::Const::str with generic decoder methodClifford Wolf2013-12-041-8/+11
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* Added proper dumping of signed/unsigned parameters to verilog backendClifford Wolf2013-11-241-4/+6
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* Renamed "placeholder" to "blackbox"Clifford Wolf2013-11-221-7/+7
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* Implemented $_DFFSR_ expression generator in verilog backendClifford Wolf2013-11-211-1/+44
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