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frontends
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aiger
/
aigerparse.cc
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Author
Age
Files
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Merge remote-tracking branch 'origin/master' into xaig
Eddie Hung
2019-06-12
1
-859
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+833
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Fix spacing from spaces to tabs
Eddie Hung
2019-06-07
1
-362
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+362
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Fix spacing (entire file is wrong anyway, will fix later)
Eddie Hung
2019-06-07
1
-3
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+3
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Remove unnecessary std::getline() for ASCII
Eddie Hung
2019-06-07
1
-3
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+0
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Fix read_aiger -- create zero driver, fix init width, parse 'b'
Eddie Hung
2019-06-07
1
-13
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+51
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Rename label
Eddie Hung
2019-05-21
1
-6
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+5
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Try again
Eddie Hung
2019-05-21
1
-4
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+10
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Fix warning
Eddie Hung
2019-05-21
1
-3
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+2
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Move clean from aigerparse to abc9
Eddie Hung
2019-04-23
1
-2
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+0
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Tidy up
Eddie Hung
2019-04-22
1
-1
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+1
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Revert "Temporarily remove 'r' extension"
Eddie Hung
2019-04-22
1
-0
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+18
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This reverts commit eaf3c247729365cec776e147f380ce59f7dccd4d.
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Temporarily remove 'r' extension
Eddie Hung
2019-04-22
1
-18
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+0
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Merge remote-tracking branch 'origin/master' into xaig
Eddie Hung
2019-04-22
1
-3
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+0
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Add log_debug() framework
Clifford Wolf
2019-04-22
1
-2
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+0
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
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read_aiger to parse 'r' extension
Eddie Hung
2019-04-18
1
-0
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+18
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Ignore a/i/o/h XAIGER extensions
Eddie Hung
2019-04-17
1
-0
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+7
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Forgot backslashes
Eddie Hung
2019-04-12
1
-1
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+1
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Handle __dummy_o__ and __const[01]__ in read_aiger not abc
Eddie Hung
2019-04-12
1
-0
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+4
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Merge branch 'xaig' of github.com:YosysHQ/yosys into xaig
Eddie Hung
2019-04-12
1
-12
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+32
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Fix inout handling for -map option
Eddie Hung
2019-04-12
1
-10
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+30
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Also cope with duplicated CIs
Eddie Hung
2019-04-12
1
-5
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+23
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Cope with an output having same name as an input (i.e. CO)
Eddie Hung
2019-04-12
1
-5
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+23
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parse_aiger() to rename all $lut cells after "clean"
Eddie Hung
2019-04-10
1
-24
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+21
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Fix spacing
Eddie Hung
2019-04-08
1
-29
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+29
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parse_xaiger() to really pass single and multi-bit inout tests
Eddie Hung
2019-02-26
1
-10
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+12
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parse_xaiger() to cope with multi bit inouts
Eddie Hung
2019-02-26
1
-0
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+11
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parse_xaiger() to untransform $inout.out output ports
Eddie Hung
2019-02-25
1
-5
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+20
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read_aiger to accept empty string for clk_name, passable only if no latches
Eddie Hung
2019-02-25
1
-0
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+2
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read_aiger to work with symbol table
Eddie Hung
2019-02-21
1
-8
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+47
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Add attribution
Eddie Hung
2019-02-21
1
-1
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+1
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Merge branch 'read_aiger' into xaig
Eddie Hung
2019-02-21
1
-2
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+7
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Fix for using POSIX basename
Eddie Hung
2019-02-19
1
-2
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+4
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Missing OSX headers?
Eddie Hung
2019-02-17
1
-0
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+5
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read_aiger to ignore line after ands for ascii, not binary
Eddie Hung
2019-02-17
1
-2
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+1
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read_aiger to not do -purge for clean
Eddie Hung
2019-02-20
1
-1
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+1
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lut/not/and suffix to be ${lut,not,and}
Eddie Hung
2019-02-20
1
-13
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+13
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read_aiger to also rename 0 index lut when wideports
Eddie Hung
2019-02-20
1
-2
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+14
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read_aiger: new naming fixes
Eddie Hung
2019-02-20
1
-5
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+5
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read_aiger to name wires with internal name, less likely to clash
Eddie Hung
2019-02-20
1
-18
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+15
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Same for ascii AIGERs too
Eddie Hung
2019-02-19
1
-6
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+13
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read_aiger to cope with non-unique POs
Eddie Hung
2019-02-19
1
-6
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+13
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read_aiger to create sane $lut names, and rename when renaming driving wire
Eddie Hung
2019-02-19
1
-2
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+11
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Add comment
Eddie Hung
2019-02-19
1
-1
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+2
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Get rid of boost dep, fix the FIXMEs for Win32?
Eddie Hung
2019-02-19
1
-14
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+14
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In read_xaiger, do not construct ConstEval for every LUT
Eddie Hung
2019-02-16
1
-1
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+1
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read_aiger to ignore output = input of same wire; also create new output for ↵
Eddie Hung
2019-02-16
1
-2
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+16
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different wire
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read_aiger to disable log_debug
Eddie Hung
2019-02-16
1
-1
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+2
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read_xaiger() to use f.read() not readsome()
Eddie Hung
2019-02-16
1
-1
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+2
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read_aiger() to cope with constant outputs, mixed wideports, do cleaning
Eddie Hung
2019-02-16
1
-8
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+130
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read_aiger with more asserts, and call clean
Eddie Hung
2019-02-15
1
-4
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+11
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