| Commit message (Expand) | Author | Age | Files | Lines |
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| * | Add "read_verilog -pwires" feature, closes #1106 | Clifford Wolf | 2019-06-19 | 1 | -1/+20 |
| * | Fixes and cleanups in AST_TECALL handling | Clifford Wolf | 2019-06-07 | 1 | -1/+31 |
| * | Merge branch 'pr_elab_sys_tasks' of https://github.com/udif/yosys into cliffo... | Clifford Wolf | 2019-06-07 | 1 | -0/+1 |
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| | * | Initial implementation of elaboration system tasks | Udi Finkelstein | 2019-05-03 | 1 | -0/+1 |
| * | | Merge branch 'master' into wandwor | Stefan Biereigel | 2019-05-27 | 1 | -3/+9 |
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| | * \ | Merge pull request #1044 from mmicko/invalid_width_range | Clifford Wolf | 2019-05-27 | 1 | -1/+2 |
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| | | * | | Give error instead of asserting for invalid range, fixes #947 | Miodrag Milanovic | 2019-05-27 | 1 | -1/+2 |
| | * | | | Added support for unsized constants, fixes #1022 | Miodrag Milanovic | 2019-05-27 | 1 | -2/+7 |
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| * | | | move wand/wor resolution into hierarchy pass | Stefan Biereigel | 2019-05-27 | 1 | -97/+14 |
| * | | | fix assignment of non-wires | Stefan Biereigel | 2019-05-23 | 1 | -16/+19 |
| * | | | fix indentation across files | Stefan Biereigel | 2019-05-23 | 1 | -58/+76 |
| * | | | implementation for assignments working | Stefan Biereigel | 2019-05-23 | 1 | -14/+79 |
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| * | | Improve write_verilog specify support | Clifford Wolf | 2019-05-04 | 1 | -0/+3 |
| * | | Merge remote-tracking branch 'origin/master' into clifford/specify | Eddie Hung | 2019-05-03 | 1 | -0/+2 |
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| | * | | Fix width detection of memory access with bit slice, fixes #974 | Clifford Wolf | 2019-05-01 | 1 | -0/+2 |
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| * | | Add $specrule cells for $setup/$hold/$skew specify rules | Clifford Wolf | 2019-04-23 | 1 | -0/+6 |
| * | | Checking and fixing specify cells in genRTLIL | Clifford Wolf | 2019-04-23 | 1 | -1/+15 |
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| * | Improve handling of "full_case" attributes | Clifford Wolf | 2019-03-14 | 1 | -0/+9 |
| * | Add support for SVA labels in read_verilog | Clifford Wolf | 2019-03-07 | 1 | -3/+9 |
| * | Fix error for wire decl in always block, fixes #763 | Clifford Wolf | 2019-03-02 | 1 | -1/+5 |
| * | Fixes related to handling of autowires and upto-ranges, fixes #814 | Clifford Wolf | 2019-02-21 | 1 | -2/+2 |
| * | Fix segfault in printing of some internal error messages | Clifford Wolf | 2019-02-21 | 1 | -2/+2 |
| * | Fix sign handling of real constants | Clifford Wolf | 2019-02-13 | 1 | -5/+4 |
| * | Various indenting fixes in AST front-end (mostly space vs tab issues) | Clifford Wolf | 2018-11-04 | 1 | -55/+33 |
| * | Improve read_verilog range out of bounds warning | Clifford Wolf | 2018-10-20 | 1 | -6/+6 |
| * | Refactor code to avoid code duplication + added comments | Ruben Undheim | 2018-10-20 | 1 | -21/+4 |
| * | Documentation improvements etc. | Ruben Undheim | 2018-10-13 | 1 | -5/+7 |
| * | Support for 'modports' for System Verilog interfaces | Ruben Undheim | 2018-10-12 | 1 | -0/+29 |
| * | Synthesis support for SystemVerilog interfaces | Ruben Undheim | 2018-10-12 | 1 | -2/+46 |
| * | Fix for issue 594. | Tom Verbeure | 2018-10-02 | 1 | -1/+2 |
| * | Convert more log_error() to log_file_error() where possible. | Henner Zeller | 2018-07-20 | 1 | -71/+69 |
| * | Use log_file_warning(), log_file_error() functions. | Henner Zeller | 2018-07-20 | 1 | -16/+16 |
| * | Provide source-location logging. | Henner Zeller | 2018-07-19 | 1 | -3/+2 |
| * | Fix handling of signed memories | Clifford Wolf | 2018-06-28 | 1 | -0/+3 |
| * | Add (* gclk *) attribute support | Clifford Wolf | 2018-06-01 | 1 | -0/+9 |
| * | Add $allconst and $allseq cell types | Clifford Wolf | 2018-02-23 | 1 | -2/+2 |
| * | Fix error handling for nested always/initial | Clifford Wolf | 2017-12-02 | 1 | -0/+2 |
| * | Fix generation of vlogtb output in yosys-smtbmc for "rand reg" and "rand cons... | Clifford Wolf | 2017-06-07 | 1 | -0/+7 |
| * | Add $live and $fair cell types, add support for s_eventually keyword | Clifford Wolf | 2017-02-25 | 1 | -1/+6 |
| * | Add $cover cell type and SVA cover() support | Clifford Wolf | 2017-02-04 | 1 | -0/+2 |
| * | Some fixes in handling of signed arrays | Clifford Wolf | 2016-11-01 | 1 | -0/+1 |
| * | Added $anyseq cell type | Clifford Wolf | 2016-10-14 | 1 | -2/+2 |
| * | Added $global_clock verilog syntax support for creating $ff cells | Clifford Wolf | 2016-10-14 | 1 | -4/+11 |
| * | Added $past, $stable, $rose, $fell SVA functions | Clifford Wolf | 2016-09-19 | 1 | -0/+10 |
| * | Added assertpmux | Clifford Wolf | 2016-09-07 | 1 | -0/+1 |
| * | Added $anyconst support to yosys-smtbmc | Clifford Wolf | 2016-08-30 | 1 | -0/+2 |
| * | Removed $aconst cell type | Clifford Wolf | 2016-08-30 | 1 | -3/+3 |
| * | Removed $predict again | Clifford Wolf | 2016-08-28 | 1 | -2/+0 |
| * | Another bugfix in mem2reg code | Clifford Wolf | 2016-08-21 | 1 | -0/+2 |
| * | Optimize memory address port width in wreduce and memory_collect, not verilog... | Clifford Wolf | 2016-08-19 | 1 | -4/+8 |
