| Commit message (Expand) | Author | Age | Files | Lines |
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| * | Fix $global_clock handling vs autowire | Clifford Wolf | 2019-03-02 | 1 | -1/+1 |
| * | Fix $readmem[hb] for mem2reg memories, fixes #785 | Clifford Wolf | 2019-03-02 | 1 | -0/+35 |
| * | Use mem2reg on memories that only have constant-index write ports | Clifford Wolf | 2019-03-01 | 1 | -0/+11 |
| * | Fix handling of defparam for when default_nettype is none | Clifford Wolf | 2019-02-24 | 1 | -0/+4 |
| * | Fixes related to handling of autowires and upto-ranges, fixes #814 | Clifford Wolf | 2019-02-21 | 1 | -7/+10 |
| * | Fix handling of expression width in $past, fixes #810 | Clifford Wolf | 2019-02-21 | 1 | -1/+1 |
| * | Fix segfault in AST simplify | Clifford Wolf | 2018-12-18 | 1 | -0/+5 |
| * | Make return value of $clog2 signed | Sylvain Munaut | 2018-11-24 | 1 | -1/+1 |
| * | Various indenting fixes in AST front-end (mostly space vs tab issues) | Clifford Wolf | 2018-11-04 | 1 | -38/+33 |
| * | Make and dependent upon LSB only | ZipCPU | 2018-11-03 | 1 | -2/+8 |
| * | Do not generate "reg assigned in a continuous assignment" warnings for "rand ... | Clifford Wolf | 2018-11-01 | 1 | -2/+15 |
| * | Merge pull request #659 from rubund/sv_interfaces | Clifford Wolf | 2018-10-18 | 1 | -1/+1 |
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| | * | Synthesis support for SystemVerilog interfaces | Ruben Undheim | 2018-10-12 | 1 | -1/+1 |
| * | | Merge pull request #638 from udif/pr_reg_wire_error | Clifford Wolf | 2018-10-17 | 1 | -0/+12 |
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| | * | Fixed issue #630 by fixing a minor typo in the previous commit | Udi Finkelstein | 2018-09-25 | 1 | -2/+2 |
| | * | Merge branch 'master' into pr_reg_wire_error | Udi Finkelstein | 2018-09-18 | 1 | -123/+121 |
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| | * | | Fixed remaining cases where we check fo wire reg/wire incorrect assignments | Udi Finkelstein | 2018-09-18 | 1 | -0/+12 |
| * | | | Add read_verilog $changed support | Dan Gisselquist | 2018-10-01 | 1 | -1/+4 |
| * | | | Fix handling of $past 2nd argument in read_verilog | Clifford Wolf | 2018-09-30 | 1 | -1/+1 |
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| * | | Merge pull request #590 from hzeller/remaining-file-error | Clifford Wolf | 2018-08-15 | 1 | -15/+15 |
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| | * | | Fix remaining log_file_error(); emit dependent file references in new line. | Henner Zeller | 2018-07-20 | 1 | -15/+15 |
| * | | | Merge pull request #513 from udif/pr_reg_wire_error | Clifford Wolf | 2018-08-15 | 1 | -0/+42 |
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| | * | Modified errors into warnings | Udi Finkelstein | 2018-06-05 | 1 | -6/+38 |
| | * | This PR should be the base for discussion, do not merge it yet! | Udi Finkelstein | 2018-03-11 | 1 | -0/+10 |
| * | | Convert more log_error() to log_file_error() where possible. | Henner Zeller | 2018-07-20 | 1 | -54/+53 |
| * | | Use log_file_warning(), log_file_error() functions. | Henner Zeller | 2018-07-20 | 1 | -61/+60 |
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| * | Add $allconst and $allseq cell types | Clifford Wolf | 2018-02-23 | 1 | -1/+1 |
| * | Add support for "yosys -E" | Clifford Wolf | 2018-01-07 | 1 | -0/+1 |
| * | Fix error handling for nested always/initial | Clifford Wolf | 2017-12-02 | 1 | -0/+3 |
| * | Remove some dead code | Clifford Wolf | 2017-10-10 | 1 | -15/+0 |
| * | Allow $past, $stable, $rose, $fell in $global_clock blocks | Clifford Wolf | 2017-10-10 | 1 | -1/+5 |
| * | Allow $size and $bits in verilog mode, actually check test case | Clifford Wolf | 2017-09-29 | 1 | -1/+1 |
| * | $size() now works correctly for all cases! | Udi Finkelstein | 2017-09-26 | 1 | -17/+17 |
| * | $size() seems to work now with or without the optional parameter. | Udi Finkelstein | 2017-09-26 | 1 | -10/+40 |
| * | enable $bits() and $size() functions only when the SystemVerilog flag is enab... | Udi Finkelstein | 2017-09-26 | 1 | -1/+1 |
| * | Added $bits() for memories as well. | Udi Finkelstein | 2017-09-26 | 1 | -2/+26 |
| * | $size() now works with memories as well! | Udi Finkelstein | 2017-09-26 | 1 | -1/+3 |
| * | Add $size() function. At the moment it works only on expressions, not on memo... | Udi Finkelstein | 2017-09-26 | 1 | -0/+14 |
| * | Add $live and $fair cell types, add support for s_eventually keyword | Clifford Wolf | 2017-02-25 | 1 | -2/+2 |
| * | Fix incorrect "incompatible re-declaration of wire" error in tasks/functions | Clifford Wolf | 2017-02-14 | 1 | -2/+9 |
| * | Add $cover cell type and SVA cover() support | Clifford Wolf | 2017-02-04 | 1 | -2/+2 |
| * | Fix bug in AstNode::mem2reg_as_needed_pass2() | Clifford Wolf | 2017-01-15 | 1 | -0/+2 |
| * | Fixed handling of local memories in functions | Clifford Wolf | 2017-01-05 | 1 | -2/+2 |
| * | Added handling of local memories and error for local decls in unnamed blocks | Clifford Wolf | 2017-01-04 | 1 | -1/+10 |
| * | Added Verilog $rtoi and $itor support | Clifford Wolf | 2017-01-03 | 1 | -24/+30 |
| * | Added support for hierarchical defparams | Clifford Wolf | 2016-11-15 | 1 | -11/+32 |
| * | Fixed anonymous genblock object names | Clifford Wolf | 2016-11-04 | 1 | -1/+1 |
| * | Some fixes in handling of signed arrays | Clifford Wolf | 2016-11-01 | 1 | -0/+6 |
| * | Added $anyseq cell type | Clifford Wolf | 2016-10-14 | 1 | -2/+2 |
| * | Added $past, $stable, $rose, $fell SVA functions | Clifford Wolf | 2016-09-19 | 1 | -2/+131 |
