iCE40/yosys - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
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*	Added basic support for $expect cells	Clifford Wolf	2016-07-13	4	-7/+16
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*	Fixed mem assignment in left-hand-side concatenation	Clifford Wolf	2016-07-08	1	-0/+44
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*	A few modifications after pull request comments	Ruben Undheim	2016-06-18	1	-2/+2
\| \| \| \| \|	- Renamed Design::packages to Design::verilog_packages - No need to include ast.h in rtlil.h
*	Added support for SystemVerilog packages with localparam definitions	Ruben Undheim	2016-06-18	3	-1/+16
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*	Fixed procedural assignments to non-unique lvalues, e.g. {y,y} = {a,b}	Clifford Wolf	2016-05-27	1	-0/+11
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*	Fixed access-after-delete bug in mem2reg code	Clifford Wolf	2016-05-27	2	-6/+23
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*	fixed typos in error messages	Clifford Wolf	2016-05-27	1	-3/+3
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*	Include <cmath> in yosys.h	Clifford Wolf	2016-05-08	1	-9/+0
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*	Added "yosys -D" feature	Clifford Wolf	2016-04-21	1	-1/+1
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*	Fixed handling of parameters and const functions in casex/casez pattern	Clifford Wolf	2016-04-21	4	-6/+31
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*	Do not set "nosync" on task outputs, fixes #134	Clifford Wolf	2016-03-24	1	-1/+2
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*	Added support for $stop system task	Clifford Wolf	2016-03-21	1	-5/+5
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*	Added $display %m support, fixed mem leak in $display, fixes #128	Clifford Wolf	2016-03-19	1	-20/+44
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*	Fixed localparam signdness, fixes #127	Clifford Wolf	2016-03-18	1	-1/+1
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*	Set "nosync" attribute on internal task/function wires	Clifford Wolf	2016-03-18	1	-0/+1
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*	Fixed some visual studio warnings	Clifford Wolf	2016-02-13	3	-4/+4
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*	genrtlil: avoid converting SigSpec to set<SigBit> when going through ↵	Rick Altherr	2016-01-31	1	-3/+3
\| \| \| \|	removeSignalFromCaseTree()
*	Fixed handling of re-declarations of wires in tasks and functions	Clifford Wolf	2015-11-23	1	-7/+26
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*	More bugfixes in handling of parameters in tasks and functions	Clifford Wolf	2015-11-12	1	-1/+11
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*	Fixed handling of parameters and localparams in functions	Clifford Wolf	2015-11-11	2	-3/+8
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*	Import more std:: stuff into Yosys namespace	Clifford Wolf	2015-10-25	2	-32/+32
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*	Fixed complexity of assigning to vectors in constant functions	Clifford Wolf	2015-10-01	1	-0/+3
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*	Fixed detection of unconditional $readmem[hb]	Clifford Wolf	2015-09-30	1	-4/+11
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*	Bugfixes in $readmem[hb]	Clifford Wolf	2015-09-25	1	-4/+7
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*	Fixed segfault in AstNode::asReal	Clifford Wolf	2015-09-25	1	-1/+1
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*	Added read-enable to memory model	Clifford Wolf	2015-09-25	1	-0/+1
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*	Fixed AstNode::mkconst_bits() segfault on zero-sized constant	Clifford Wolf	2015-09-24	1	-1/+1
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*	Bugfix in handling of multi-dimensional memories	Clifford Wolf	2015-09-23	1	-2/+2
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*	Warning for $display/$write outside initial block	Clifford Wolf	2015-09-23	1	-7/+8
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*	Fixed multi-level prefix resolving	Clifford Wolf	2015-09-22	1	-0/+2
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*	Improvements to $display system task	Andrew Zonenberg	2015-09-19	1	-9/+22
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*	Added AST_INITIAL checks for $finish and $display	Clifford Wolf	2015-09-18	1	-2/+9
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*	Initial implementation of $display()	Andrew Zonenberg	2015-09-18	1	-1/+84
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*	Initial implementation of $finish()	Andrew Zonenberg	2015-09-18	1	-2/+8
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*	Fixed handling of memory read without address	Clifford Wolf	2015-08-22	1	-1/+1
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*	Another block of spelling fixes	Larry Doolittle	2015-08-14	1	-4/+4
\| \| \| \|	Smaller this time
*	Keep gcc from complaining about uninitialized variables	Larry Doolittle	2015-08-14	1	-2/+2
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*	Spell check (by Larry Doolittle)	Clifford Wolf	2015-08-14	3	-14/+14
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*	Added WORDS parameter to $meminit	Clifford Wolf	2015-07-31	3	-7/+67
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*	Fixed nested mem2reg	Clifford Wolf	2015-07-29	2	-4/+11
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*	Fixed trailing whitespaces	Clifford Wolf	2015-07-02	5	-12/+12
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*	Fixed handling of parameters with reversed range	Clifford Wolf	2015-06-08	1	-1/+1
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*	Fixed signedness of genvar expressions	Clifford Wolf	2015-05-29	1	-2/+2
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*	Const-fold parameter defs on-demand in AstNode::detectSignWidthWorker()	Clifford Wolf	2015-03-01	1	-2/+4
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*	Added non-std verilog assume() statement	Clifford Wolf	2015-02-26	4	-8/+12
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*	Added deep recursion warning to AST simplify	Clifford Wolf	2015-02-20	1	-1/+7
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*	Parser support for complex delay expressions	Clifford Wolf	2015-02-20	1	-1/+1
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*	Convert floating point cell parameters to strings	Clifford Wolf	2015-02-18	1	-9/+12
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*	Various fixes for memories with offsets	Clifford Wolf	2015-02-14	2	-6/+5
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*	Added "read_verilog -nomeminit" and "nomeminit" attribute	Clifford Wolf	2015-02-14	3	-6/+14
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