| Commit message (Collapse) | Author | Age | Files | Lines | ||
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| * | | Provide source-location logging. | Henner Zeller | 2018-07-19 | 1 | -3/+2 | |
| | | | | | | | | | | | | | | | | | o Provide log_file_warning() and log_file_error() that prefix the log message with <filename>:<lineno>: to be easily picked up by IDEs that need to step through errors. o Simplify some duplicate logging code in kernel/log.cc o Use the new log functions in genrtlil. | |||||
| * | | Fix handling of signed memories | Clifford Wolf | 2018-06-28 | 1 | -0/+3 | |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | Add (* gclk *) attribute support | Clifford Wolf | 2018-06-01 | 1 | -0/+9 | |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | Replace -ignore_redef with -[no]overwrite | Clifford Wolf | 2018-05-03 | 2 | -6/+14 | |
| |/ | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | Add $allconst and $allseq cell types | Clifford Wolf | 2018-02-23 | 2 | -3/+3 | |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | Add support for "yosys -E" | Clifford Wolf | 2018-01-07 | 1 | -0/+1 | |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | Bugfix in hierarchy handling of blackbox module ports | Clifford Wolf | 2018-01-05 | 2 | -2/+2 | |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | Fix error handling for nested always/initial | Clifford Wolf | 2017-12-02 | 2 | -0/+5 | |
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| * | Remove some dead code | Clifford Wolf | 2017-10-10 | 1 | -15/+0 | |
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| * | Allow $past, $stable, $rose, $fell in $global_clock blocks | Clifford Wolf | 2017-10-10 | 1 | -1/+5 | |
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| * | Turned a few member functions into const, esp. dumpAst(), dumpVlog(). | Udi Finkelstein | 2017-09-30 | 2 | -14/+14 | |
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| * | Allow $size and $bits in verilog mode, actually check test case | Clifford Wolf | 2017-09-29 | 1 | -1/+1 | |
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| * | $size() now works correctly for all cases! | Udi Finkelstein | 2017-09-26 | 1 | -17/+17 | |
| | | | | | It seems the issues was that AST_MULTIRANGE is converted into a multirange_dimensions[] array on the AST_MEMORY node directly. | |||||
| * | $size() seems to work now with or without the optional parameter. | Udi Finkelstein | 2017-09-26 | 1 | -10/+40 | |
| | | | | | Multidimensional arrays still don't work. I suspect the problem is that the array is flattened into a 1D array before $size() is evaluated. | |||||
| * | enable $bits() and $size() functions only when the SystemVerilog flag is ↵ | Udi Finkelstein | 2017-09-26 | 1 | -1/+1 | |
| | | | | | enabled for read_verilog | |||||
| * | Added $bits() for memories as well. | Udi Finkelstein | 2017-09-26 | 1 | -2/+26 | |
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| * | $size() now works with memories as well! | Udi Finkelstein | 2017-09-26 | 1 | -1/+3 | |
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| * | Add $size() function. At the moment it works only on expressions, not on ↵ | Udi Finkelstein | 2017-09-26 | 1 | -0/+14 | |
| | | | | | memories. | |||||
| * | Fix generation of vlogtb output in yosys-smtbmc for "rand reg" and "rand ↵ | Clifford Wolf | 2017-06-07 | 1 | -0/+7 | |
| | | | | | const reg" | |||||
| * | Add $live and $fair cell types, add support for s_eventually keyword | Clifford Wolf | 2017-02-25 | 4 | -3/+12 | |
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| * | Preserve string parameters | Clifford Wolf | 2017-02-23 | 1 | -2/+8 | |
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| * | Fix incorrect "incompatible re-declaration of wire" error in tasks/functions | Clifford Wolf | 2017-02-14 | 1 | -2/+9 | |
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| * | Add $cover cell type and SVA cover() support | Clifford Wolf | 2017-02-04 | 4 | -2/+6 | |
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| * | Fix bug in AstNode::mem2reg_as_needed_pass2() | Clifford Wolf | 2017-01-15 | 1 | -0/+2 | |
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| * | Fixed handling of local memories in functions | Clifford Wolf | 2017-01-05 | 1 | -2/+2 | |
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| * | Added handling of local memories and error for local decls in unnamed blocks | Clifford Wolf | 2017-01-04 | 1 | -1/+10 | |
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| * | Added Verilog $rtoi and $itor support | Clifford Wolf | 2017-01-03 | 1 | -24/+30 | |
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| * | Added support for hierarchical defparams | Clifford Wolf | 2016-11-15 | 2 | -13/+39 | |
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| * | Remember global declarations and defines accross read_verilog calls | Clifford Wolf | 2016-11-15 | 1 | -4/+2 | |
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| * | Fixed anonymous genblock object names | Clifford Wolf | 2016-11-04 | 1 | -1/+1 | |
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| * | Some fixes in handling of signed arrays | Clifford Wolf | 2016-11-01 | 2 | -0/+7 | |
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| * | Added avail params to ilang format, check module params in 'hierarchy -check' | Clifford Wolf | 2016-10-22 | 1 | -2/+7 | |
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| * | Added $anyseq cell type | Clifford Wolf | 2016-10-14 | 2 | -4/+4 | |
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| * | Added $global_clock verilog syntax support for creating $ff cells | Clifford Wolf | 2016-10-14 | 1 | -4/+11 | |
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| * | Added $past, $stable, $rose, $fell SVA functions | Clifford Wolf | 2016-09-19 | 2 | -2/+141 | |
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| * | Added assertpmux | Clifford Wolf | 2016-09-07 | 1 | -0/+1 | |
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| * | Avoid creation of bogus initial blocks for assert/assume in always @* | Clifford Wolf | 2016-09-06 | 3 | -1/+13 | |
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| * | Added $anyconst support to yosys-smtbmc | Clifford Wolf | 2016-08-30 | 1 | -0/+2 | |
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| * | Removed $aconst cell type | Clifford Wolf | 2016-08-30 | 2 | -5/+5 | |
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| * | Removed $predict again | Clifford Wolf | 2016-08-28 | 4 | -6/+2 | |
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| * | Fixed bug with memories that do not have a down-to-zero data width | Clifford Wolf | 2016-08-22 | 1 | -2/+13 | |
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| * | Another bugfix in mem2reg code | Clifford Wolf | 2016-08-21 | 3 | -7/+31 | |
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| * | Minor improvements to AstNode::dumpAst() and AstNode::dumpVlog() | Clifford Wolf | 2016-08-21 | 1 | -4/+15 | |
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| * | Fixed finish_addr handling in $readmemh/$readmemb | Clifford Wolf | 2016-08-20 | 1 | -3/+3 | |
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| * | Optimize memory address port width in wreduce and memory_collect, not ↵ | Clifford Wolf | 2016-08-19 | 2 | -4/+13 | |
| | | | | | verilog front-end | |||||
| * | Only allow posedge/negedge with 1 bit wide signals | Clifford Wolf | 2016-08-10 | 1 | -0/+2 | |
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| * | Added $anyconst and $aconst | Clifford Wolf | 2016-07-27 | 2 | -0/+49 | |
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| * | Added "read_verilog -dump_rtlil" | Clifford Wolf | 2016-07-27 | 2 | -8/+21 | |
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| * | Using $initstate in "initial assume" and "initial assert" | Clifford Wolf | 2016-07-21 | 1 | -1/+6 | |
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| * | Added $initstate cell type and vlog function | Clifford Wolf | 2016-07-21 | 1 | -0/+24 | |
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index : iCE40/yosys | |
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