iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Fixed segfault on invalid verilog constant 1'b_	Clifford Wolf	2015-09-22	1	-1/+1
*	Small corrections to const2ast warning messages	Clifford Wolf	2015-08-17	1	-2/+2
*	Check base-n literals only contain valid digits	Florian Zeitz	2015-08-17	1	-0/+3
*	Warn on literals exceeding the specified bit width	Florian Zeitz	2015-08-17	1	-34/+39
*	Another block of spelling fixes	Larry Doolittle	2015-08-14	1	-1/+1
*	Fixed handling of [a-fxz?] in decimal constants	Clifford Wolf	2015-08-11	1	-2/+7
*	Fixed trailing whitespaces	Clifford Wolf	2015-07-02	1	-2/+2
*	Fixed two minor bugs in constant parsing	Clifford Wolf	2014-11-24	1	-1/+5
*	Added warning for use of 'z' constants in HDL	Clifford Wolf	2014-11-14	1	-1/+9
*	Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace	Clifford Wolf	2014-07-31	1	-0/+4
*	Using log_assert() instead of assert()	Clifford Wolf	2014-07-28	1	-2/+1
*	Improved parsing of large integer constants	Clifford Wolf	2014-06-15	1	-11/+28
*	Fixed handling of unsized constants in verilog frontend	Clifford Wolf	2014-01-24	1	-2/+2
*	Major redesign of expr width/sign detecion (verilog/ast frontend)	Clifford Wolf	2013-07-09	1	-1/+1
*	Added SAT generator and simple sat_solve command	Clifford Wolf	2013-06-07	1	-3/+2
*	initial import	Clifford Wolf	2013-01-05	1	-0/+197