iCE40/yosys - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
*	Added handling of real-valued parameters/localparams	Clifford Wolf	2014-06-14	1	-2/+3
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*	Added Verilog lexer and parser support for real values	Clifford Wolf	2014-06-13	1	-0/+10
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*	Added read_verilog -sv options, added support for bit, logic,	Clifford Wolf	2014-06-12	1	-1/+16
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*	added while and repeat support to verilog parser	Clifford Wolf	2014-06-06	1	-0/+2
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*	Fixed clang -Wdeprecated-register warnings	Clifford Wolf	2014-04-20	1	-0/+5
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*	Added support for `line compiler directive	Clifford Wolf	2014-03-11	1	-0/+11
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*	Added Verilog support for "`default_nettype none"	Clifford Wolf	2014-02-17	1	-0/+12
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*	Added Verilog parser support for asserts	Clifford Wolf	2014-01-19	1	-0/+2
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*	Added proper === and !== support in constant expressions	Clifford Wolf	2013-12-27	1	-2/+2
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*	Enable {* .. *} feature per default (removes dependency to REJECT feature in ↵	Clifford Wolf	2013-11-22	1	-6/+2
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*	Implemented indexed part selects	Clifford Wolf	2013-11-20	1	-0/+3
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*	Added "synthesis" in (synopsys\|synthesis) comment support	Clifford Wolf	2013-11-20	1	-6/+6
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*	fixed Verilog parser filename and line numbering issue with include files	Johann Glaser	2013-08-21	1	-0/+2
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*	Added support for notif0/notif1 primitives	Johann Glaser	2013-08-20	1	-1/+1
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*	Added support for bufif0/bufif1 primitives	Clifford Wolf	2013-08-19	1	-1/+1
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*	Added defparam support to Verilog/AST frontend	Clifford Wolf	2013-07-04	1	-1/+2
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*	More fixes for bugs found using xsthammer	Clifford Wolf	2013-06-13	1	-2/+2
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*	Further improved and extended xsthammer	Clifford Wolf	2013-06-11	1	-0/+1
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*	Added support for verilog === operator	Clifford Wolf	2013-05-07	1	-0/+2
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*	Improvements and bugfixes for generate blocks with local signals	Clifford Wolf	2013-03-26	1	-1/+1
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*	initial import	Clifford Wolf	2013-01-05	1	-0/+264