iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	fixed parsing of constant with comment between size and value	Clifford Wolf	2014-07-02	1	-0/+7
*	Fixed parsing of TOK_INTEGER (implies TOK_SIGNED)	Clifford Wolf	2014-06-16	1	-5/+11
*	Added handling of real-valued parameters/localparams	Clifford Wolf	2014-06-14	1	-5/+12
*	Added Verilog lexer and parser support for real values	Clifford Wolf	2014-06-13	1	-3/+14
*	Added read_verilog -sv options, added support for bit, logic,	Clifford Wolf	2014-06-12	1	-2/+8
*	Add support for cell arrays	Clifford Wolf	2014-06-07	1	-0/+7
*	made the generate..endgenrate keywords optional	Clifford Wolf	2014-06-06	1	-4/+8
*	added while and repeat support to verilog parser	Clifford Wolf	2014-06-06	1	-1/+27
*	Replaced depricated %name-prefix= bison directive	Clifford Wolf	2014-04-20	1	-1/+1
*	Added Verilog support for "`default_nettype none"	Clifford Wolf	2014-02-17	1	-0/+1
*	Added support for functions returning integer	Clifford Wolf	2014-02-12	1	-2/+12
*	Added constant size expression support of sized constants	Clifford Wolf	2014-02-01	1	-0/+22
*	Added Verilog parser support for asserts	Clifford Wolf	2014-01-19	1	-3/+8
*	Added proper === and !== support in constant expressions	Clifford Wolf	2013-12-27	1	-1/+9
*	Added AstNode::mkconst_str API	Clifford Wolf	2013-12-05	1	-12/+1
*	Various improvements in support for generate statements	Clifford Wolf	2013-12-04	1	-4/+40
*	Added support for local regs in named blocks	Clifford Wolf	2013-12-04	1	-2/+5
*	Improved handling of initialized registers	Clifford Wolf	2013-11-23	1	-10/+10
*	Implemented indexed part selects	Clifford Wolf	2013-11-20	1	-0/+11
*	Implemented part/bit select on memory read	Clifford Wolf	2013-11-20	1	-2/+12
*	Added init= attribute for fpga-style reset values	Clifford Wolf	2013-11-20	1	-6/+19
*	Fixed parsing of module arguments when one type is used for many args	Clifford Wolf	2013-11-19	1	-3/+10
*	Fixed parsing of "parameter integer"	Clifford Wolf	2013-11-13	1	-2/+2
*	Various fixes for correct parameter support	Clifford Wolf	2013-11-07	1	-26/+52
*	Fixed handling of boolean attributes (frontends)	Clifford Wolf	2013-10-24	1	-2/+2
*	Fixed handling of boolean attributes (kernel)	Clifford Wolf	2013-10-24	1	-1/+1
*	Added defparam support to Verilog/AST frontend	Clifford Wolf	2013-07-04	1	-9/+39
*	More fixes for bugs found using xsthammer	Clifford Wolf	2013-06-13	1	-2/+12
*	Added SAT generator and simple sat_solve command	Clifford Wolf	2013-06-07	1	-0/+2
*	Added AST_INITIAL (before verilog "initial" was mapped to AST_ALWAYS)	Clifford Wolf	2013-03-31	1	-1/+1
*	Tiny fixes to verilog parser	Clifford Wolf	2013-03-23	1	-1/+6
*	Added support for verilog genblock[index].member syntax	Clifford Wolf	2013-02-26	1	-10/+16
*	Added support for "always @(*)"	Clifford Wolf	2013-01-16	1	-0/+3
*	initial import	Clifford Wolf	2013-01-05	1	-0/+1074