| Commit message (Expand) | Author | Age | Files | Lines |
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| * | sv: fix support wire and var data type modifiers | Zachary Snow | 2021-01-20 | 1 | -9/+23 |
| * | Parse package user type in module port list | Lukasz Dalek | 2021-01-18 | 1 | -30/+32 |
| * | sv: complete support for implied task/function port directions | Zachary Snow | 2020-12-31 | 1 | -0/+10 |
| * | Ignore empty parameters in Verilog module instantiations | Claire Xenia Wolf | 2020-10-01 | 1 | -0/+3 |
| * | Rewrite multirange arrays sizes [n] as [n-1:0] | Lukasz Dalek | 2020-08-03 | 1 | -2/+11 |
| * | Use %precedence in verilog_parser.y | Claire Wolf | 2020-07-15 | 1 | -4/+4 |
| * | Fix bison warnings for missing %empty | Claire Wolf | 2020-07-15 | 1 | -59/+52 |
| * | Add missing semicolons | Kamil Rakoczy | 2020-07-15 | 1 | -5/+5 |
| * | Fix S/R conflicts | Kamil Rakoczy | 2020-07-10 | 1 | -1/+2 |
| * | Fix R/R conflicts | Kamil Rakoczy | 2020-07-10 | 1 | -10/+1 |
| * | Revert "Revert PRs #2203 and #2244." | Kamil Rakoczy | 2020-07-10 | 1 | -10/+19 |
| * | Revert PRs #2203 and #2244. | whitequark | 2020-07-09 | 1 | -19/+10 |
| * | Support logic typed parameters | Lukasz Dalek | 2020-07-06 | 1 | -7/+10 |
| * | Merge pull request #2203 from antmicro/fix-grammar | clairexen | 2020-07-01 | 1 | -4/+10 |
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| | * | Parse macro call attached semicolon as empty expression | Lukasz Dalek | 2020-06-26 | 1 | -1/+1 |
| | * | Fix integer signing grammar | Lukasz Dalek | 2020-06-26 | 1 | -3/+9 |
| * | | Merge pull request #2179 from splhack/static-cast | clairexen | 2020-07-01 | 1 | -0/+19 |
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| | * | | static cast: support changing size and signedness | Kazuki Sakamoto | 2020-06-19 | 1 | -0/+19 |
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| * | | Merge pull request #2188 from antmicro/missing-operators | whitequark | 2020-06-26 | 1 | -2/+43 |
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| | * | | Support missing sub-assign and and-assign operators | Kamil Rakoczy | 2020-06-25 | 1 | -2/+19 |
| | * | | Support missing xor-assign operator | Lukasz Dalek | 2020-06-24 | 1 | -1/+9 |
| | * | | Add plus-assignment operator | Kamil Rakoczy | 2020-06-24 | 1 | -1/+9 |
| | * | | Add or-assignment operator | Kamil Rakoczy | 2020-06-24 | 1 | -1/+9 |
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| * | | Support optional labels at the end of package definition | Lukasz Dalek | 2020-06-24 | 1 | -1/+1 |
| * | | Support optional labels at the end of module definition | Lukasz Dalek | 2020-06-24 | 1 | -1/+1 |
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| * | MSVC cannot omit operand in conditional | Anonymous Maarten | 2020-06-17 | 1 | -1/+1 |
| * | Support packed arrays in struct/union. | Peter Crozier | 2020-06-07 | 1 | -5/+5 |
| * | Merge branch 'master' into struct | Peter Crozier | 2020-06-03 | 1 | -31/+48 |
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| | * | verilog: move attr from simple_behav_stmt to its children to attach | Eddie Hung | 2020-05-25 | 1 | -13/+17 |
| | * | verilog: do not warn for attributes on null statements | Eddie Hung | 2020-05-25 | 1 | -2/+0 |
| | * | verilog: handle empty generate statement by removing gen_stmt_or_null... | Eddie Hung | 2020-05-25 | 1 | -7/+8 |
| | * | verilog: fix #2037 by permitting (and freeing) attributes on null stmt | Eddie Hung | 2020-05-25 | 1 | -1/+5 |
| | * | Merge pull request #2057 from YosysHQ/eddie/fix_task_attr | Eddie Hung | 2020-05-21 | 1 | -11/+9 |
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| | | * | Update frontends/verilog/verilog_parser.y | Eddie Hung | 2020-05-21 | 1 | -1/+1 |
| | | * | verilog: attributes before task enable (but 13 s/r conflicts) | Eddie Hung | 2020-05-14 | 1 | -10/+8 |
| | * | | verilog: default to input in sv mode if task/func has no dir ... | Eddie Hung | 2020-05-13 | 1 | -2/+10 |
| | * | | verilog: error out when non-ANSI task/func arguments | Eddie Hung | 2020-05-11 | 1 | -1/+5 |
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| * | | Allow structs within structs. | Peter Crozier | 2020-05-12 | 1 | -7/+18 |
| * | | Generalise structs and add support for packed unions. | Peter Crozier | 2020-05-12 | 1 | -16/+34 |
| * | | Implement SV structs. | Peter Crozier | 2020-05-08 | 1 | -101/+180 |
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| * | Merge pull request #2005 from YosysHQ/claire/fix1990 | Claire Wolf | 2020-05-07 | 1 | -2/+2 |
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| | * | Add AST_SELFSZ and improve handling of bit slices | Claire Wolf | 2020-05-02 | 1 | -2/+2 |
| * | | Merge pull request #2028 from zachjs/master | Eddie Hung | 2020-05-06 | 1 | -1/+6 |
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| | * | | verilog: allow null gen-if then block | Zachary Snow | 2020-05-06 | 1 | -1/+6 |
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| * | | Merge pull request #2025 from YosysHQ/eddie/frontend_cleanup | Eddie Hung | 2020-05-05 | 1 | -13/+13 |
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| | * | | frontend: cleanup to use more ID::*, more dict<> instead of map<> | Eddie Hung | 2020-05-04 | 1 | -13/+13 |
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| * | | Merge pull request #2024 from YosysHQ/eddie/primitive_src | Eddie Hung | 2020-05-05 | 1 | -1/+3 |
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| | * | | verilog: set src attribute for primitives | Eddie Hung | 2020-05-04 | 1 | -1/+3 |
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| * / | verilog: fix specify src attribute | Eddie Hung | 2020-05-04 | 1 | -18/+20 |
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| * | Set Verilog source location for explicit blocks (`begin` ... `end`). | Alberto Gonzalez | 2020-04-17 | 1 | -0/+1 |
