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* Build pkg_user_types before parsing in case of changes in the design.Peter Crozier2020-03-221-6/+3
* Clear pkg_user_types if no packages following a 'design -reset-vlog'.Peter2020-03-222-0/+5
* Parser changes to support typedef.Peter2020-03-224-10/+88
* Merge pull request #1787 from YosysHQ/mmicko/lexer_depsMiodrag Milanović2020-03-191-1/+1
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| * Add one mode dependencyMiodrag Milanovic2020-03-191-1/+1
* | Merge pull request #1775 from huaixv/asserts_locationsN. Engelhardt2020-03-191-7/+30
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| * Add precise locations for assertshuaixv2020-03-191-7/+30
* | Add AST node source location information in a couple more parser rules.Alberto Gonzalez2020-03-171-0/+2
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* Merge pull request #1759 from zeldin/constant_with_comment_reduxMiodrag Milanović2020-03-142-19/+43
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| * refixed parsing of constant with comment between size and valueMarcus Comstedt2020-03-112-19/+43
* | verilog: also set location for simple_behavioral_stmtEddie Hung2020-03-101-0/+4
* | Set AST source locations in more parser rules.Alberto Gonzalez2020-03-101-2/+49
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* Fix partsel expr bit width handling and add test caseClaire Wolf2020-03-081-4/+6
* Fix bison warning for "pure-parser" optionClaire Wolf2020-03-031-1/+1
* Closes #1717. Add more precise Verilog source location information to AST and...Alberto Gonzalez2020-02-234-32/+131
* Merge pull request #1703 from YosysHQ/eddie/specify_improveEddie Hung2020-02-212-29/+81
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| * verilog: add support for more delays than just rise/fallEddie Hung2020-02-191-1/+40
| * verilog: ignore ranges too without -specifyEddie Hung2020-02-131-1/+2
| * verilog: improve specify support when not in -specify modeEddie Hung2020-02-131-13/+7
| * verilog: ignore '&&&' when not in -specify modeEddie Hung2020-02-132-5/+6
| * specify: system timing checks to accept min:typ:max tripleEddie Hung2020-02-131-12/+29
* | Merge pull request #1642 from jjj11x/jjj11x/sv-enumClaire Wolf2020-02-201-2/+104
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| * add attributes for enumerated values in ilangJeff Wang2020-02-171-1/+8
| * lexer doesn't seem to return TOK_REG for logic anymoreJeff Wang2020-01-161-3/+4
| * allow enum typedefsJeff Wang2020-01-161-1/+6
| * partial rebase of PeterCrozier's enum work onto current masterJeff Wang2020-01-161-1/+90
* | Merge pull request #1679 from thasti/delay-parsingN. Engelhardt2020-02-131-2/+2
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| * | correct wire declaration grammar for #1614Stefan Biereigel2020-02-031-2/+2
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* | sv: Improve handling of wildcard port connectionsDavid Shah2020-02-022-4/+6
* | hierarchy: Resolve SV wildcard port connectionsDavid Shah2020-02-021-1/+1
* | sv: Add lexing and parsing of .* (wildcard port conns)David Shah2020-02-022-1/+6
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* Fixed some missing "verilog_" in documentationRodrigo Alejandro Melo2019-12-132-2/+2
* kernel: require \B_SIGNED=0 on $shl, $sshl, $shr, $sshr.whitequark2019-12-041-5/+5
* sv: Correct parsing of always_comb, always_ff and always_latchDavid Shah2019-11-212-5/+40
* Add check for valid macro names in macro definitionsClifford Wolf2019-11-071-7/+11
* Add "verilog_defines -list" and "verilog_defines -reset"Clifford Wolf2019-10-211-0/+16
* Use "(id)" instead of "id" for types as temporary hackClifford Wolf2019-10-141-11/+69
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| * sv: Disambiguate interface portsDavid Shah2019-10-031-3/+19
| * sv: Fix memories of typedefsDavid Shah2019-10-031-1/+1
| * sv: Add %expectDavid Shah2019-10-031-0/+1
| * sv: Add support for memory typedefsDavid Shah2019-10-031-1/+19
| * sv: Fix typedef parametersDavid Shah2019-10-031-4/+17
| * sv: Switch parser to glr, prep for typedefDavid Shah2019-10-031-4/+34
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* Fix handling of z_digit "?" and fix optimization of cmp with "z"Clifford Wolf2019-09-131-5/+1
* Fix lexing of integer literals without radixClifford Wolf2019-09-131-1/+1
* Fix lexing of integer literals, fixes #1364Clifford Wolf2019-09-122-3/+3
* substr() -> compare()Eddie Hung2019-08-071-4/+4
* RTLIL::S{0,1} -> State::S{0,1}Eddie Hung2019-08-071-12/+12
* verilog_lexer: Increase YY_BUF_SIZE to 65536David Shah2019-07-261-0/+3
* Merge pull request #1147 from YosysHQ/clifford/fix1144Clifford Wolf2019-07-031-81/+14
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