aboutsummaryrefslogtreecommitdiffstats
path: root/frontends/verilog
Commit message (Collapse)AuthorAgeFilesLines
...
* Merge branch 'master' into structPeter Crozier2020-06-032-38/+56
|\
| * Merge pull request #2033 from boqwxp/cleanup-verilog-lexerwhitequark2020-05-291-6/+5
| |\ | | | | | | verilog: Move lexer location variables from global namespace to `VERILOG_FRONTEND` namespace.
| | * verilog: Move lexer location variables from global namespace to ↵Alberto Gonzalez2020-05-061-6/+5
| | | | | | | | | | | | `VERILOG_FRONTEND` namespace.
| * | Silence spurious warning in Verilog lexer when compiling with GCCRupert Swarbrick2020-05-261-1/+3
| | | | | | | | | | | | | | | | | | | | | The chosen value shouldn't have any effect. I considered something clearly wrong like -1, but there's no checking inside the generated lexer, and I suspect this will cause even weirder bugs if triggered than just setting it to INITIAL.
| * | verilog: move attr from simple_behav_stmt to its children to attachEddie Hung2020-05-251-13/+17
| | |
| * | verilog: do not warn for attributes on null statementsEddie Hung2020-05-251-2/+0
| | |
| * | verilog: handle empty generate statement by removing gen_stmt_or_null...Eddie Hung2020-05-251-7/+8
| | | | | | | | | | | | | | | ... rule which causes a s/r conflict. Now we get an empty genblock, which should be okay.
| * | verilog: fix #2037 by permitting (and freeing) attributes on null stmtEddie Hung2020-05-251-1/+5
| | |
| * | Merge pull request #2057 from YosysHQ/eddie/fix_task_attrEddie Hung2020-05-211-11/+9
| |\ \ | | | | | | | | verilog: support attributes before (not after) task identifier (but 13 s/r conflicts)
| | * | Update frontends/verilog/verilog_parser.yEddie Hung2020-05-211-1/+1
| | | | | | | | | | | | Co-authored-by: Alberto Gonzalez <61295559+boqwxp@users.noreply.github.com>
| | * | verilog: attributes before task enable (but 13 s/r conflicts)Eddie Hung2020-05-141-10/+8
| | | |
| * | | verilog: default to input in sv mode if task/func has no dir ...Eddie Hung2020-05-131-2/+10
| | | | | | | | | | | | | | | | otherwise error
| * | | verilog: error out when non-ANSI task/func argumentsEddie Hung2020-05-111-1/+5
| |/ /
* | | Allow structs within structs.Peter Crozier2020-05-121-7/+18
| | |
* | | Generalise structs and add support for packed unions.Peter Crozier2020-05-122-18/+38
| | |
* | | Implement SV structs.Peter Crozier2020-05-082-102/+186
|/ /
* | Merge pull request #2005 from YosysHQ/claire/fix1990Claire Wolf2020-05-071-2/+2
|\ \ | | | | | | Add "nowrshmsk" attribute, fix shift-and-mask bit slice write for signed offset
| * | Add AST_SELFSZ and improve handling of bit slicesClaire Wolf2020-05-021-2/+2
| | | | | | | | | | | | Signed-off-by: Claire Wolf <claire@symbioticeda.com>
* | | Merge pull request #2028 from zachjs/masterEddie Hung2020-05-061-1/+6
|\ \ \ | |_|/ |/| | verilog: allow null gen-if then block
| * | verilog: allow null gen-if then blockZachary Snow2020-05-061-1/+6
| |/
* | Merge pull request #2025 from YosysHQ/eddie/frontend_cleanupEddie Hung2020-05-053-15/+15
|\ \ | | | | | | frontend: cleanup to use more ID::*, more dict<> instead of map<>
| * | frontend: cleanup to use more ID::*, more dict<> instead of map<>Eddie Hung2020-05-043-15/+15
| |/
* | Merge pull request #2024 from YosysHQ/eddie/primitive_srcEddie Hung2020-05-051-1/+3
|\ \ | | | | | | verilog: set src attribute for primitives
| * | verilog: set src attribute for primitivesEddie Hung2020-05-041-1/+3
| |/
* / verilog: fix specify src attributeEddie Hung2020-05-041-18/+20
|/
* Set Verilog source location for explicit blocks (`begin` ... `end`).Alberto Gonzalez2020-04-171-0/+1
|
* Add Verilog source location information to `AST_POSEDGE` and `AST_NEGEDGE` ↵Alberto Gonzalez2020-04-171-0/+2
| | | | nodes.
* Add location information to `AST_CONSTANT` nodes.Alberto Gonzalez2020-04-161-0/+3
|
* Merge pull request #1879 from jjj11x/jjj11x/package_declwhitequark2020-04-141-1/+2
|\ | | | | support using previously declared types/localparams/parameters in package
| * support using previously declared types/localparams/params in packageJeff Wang2020-04-071-1/+2
| | | | | | | | | | | | | | (parameters in systemverilog packages can't actually be overridden, so allowing parameters in addition to localparams doesn't actually add any new functionality, but it's useful to be able to use the parameter keyword also)
* | verilog: Fix write to deleted objectDavid Shah2020-04-121-1/+0
|/ | | | Signed-off-by: David Shah <dave@ds0.me>
* Merge pull request #1767 from YosysHQ/eddie/idstringsEddie Hung2020-04-021-27/+27
|\ | | | | IdString: use more ID::*, make them easier to use, speed up IdString::in()
| * kernel: big fat patch to use more ID::*, otherwise ID(*)Eddie Hung2020-04-021-5/+5
| |
| * kernel: use more ID::*Eddie Hung2020-04-021-22/+22
| |
* | Merge pull request #1846 from dh73/ast_feClaire Wolf2020-04-021-0/+3
|\ \ | |/ |/| Adding error message for when size (width) of number literal is zero
| * Replacing log_error for log_file_error due consistencyDiego H2020-03-311-2/+1
| |
| * Adding error message for when size (width) of number literal is zeroDiego H2020-03-301-0/+4
| |
* | verilog: Add location info for generate constructsDavid Shah2020-04-011-0/+6
|/ | | | Signed-off-by: David Shah <dave@ds0.me>
* Merge pull request #1811 from PeterCrozier/typedef_scopeN. Engelhardt2020-03-304-41/+81
|\ | | | | Support module/package/interface/block scope for typedef names.
| * Inline productions to follow house style.Peter Crozier2020-03-271-33/+29
| |
| * Error duplicate declarations of a typedef name in the same scope.Peter Crozier2020-03-242-3/+11
| |
| * Support module/package/interface/block scope for typedef names.Peter Crozier2020-03-234-20/+56
| |
* | Add support for SystemVerilog-style `define to Verilog frontendRupert Swarbrick2020-03-274-149/+578
|/ | | | | | | | | | | | | | | | | | | | | | | | | | | This patch should support things like `define foo(a, b = 3, c) a+b+c `foo(1, ,2) which will evaluate to 1+3+2. It also spots mistakes like `foo(1) (the 3rd argument doesn't have a default value, so a call site is required to set it). Most of the patch is a simple parser for the format in preproc.cc, but I've also taken the opportunity to wrap up the "name -> definition" map in a type, rather than use multiple std::map's. Since this type needs to be visible to code that touches defines, I've pulled it (and the frontend_verilog_preproc declaration) out into a new file at frontends/verilog/preproc.h and included that where necessary. Finally, the patch adds a few tests in tests/various to check that we are parsing everything correctly.
* Build pkg_user_types before parsing in case of changes in the design.Peter Crozier2020-03-221-6/+3
|
* Clear pkg_user_types if no packages following a 'design -reset-vlog'.Peter2020-03-222-0/+5
|
* Parser changes to support typedef.Peter2020-03-224-10/+88
|
* Merge pull request #1787 from YosysHQ/mmicko/lexer_depsMiodrag Milanović2020-03-191-1/+1
|\ | | | | Add dependency to verilog_lexer.cc
| * Add one mode dependencyMiodrag Milanovic2020-03-191-1/+1
| |
* | Merge pull request #1775 from huaixv/asserts_locationsN. Engelhardt2020-03-191-7/+30
|\ \ | |/ |/| Add precise locations for asserts
| * Add precise locations for assertshuaixv2020-03-191-7/+30
| |
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-05 16:55:14 +0000