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* | verilog: Fix write to deleted objectDavid Shah2020-04-121-1/+0
|/ | | | Signed-off-by: David Shah <dave@ds0.me>
* Merge pull request #1767 from YosysHQ/eddie/idstringsEddie Hung2020-04-021-27/+27
|\ | | | | IdString: use more ID::*, make them easier to use, speed up IdString::in()
| * kernel: big fat patch to use more ID::*, otherwise ID(*)Eddie Hung2020-04-021-5/+5
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| * kernel: use more ID::*Eddie Hung2020-04-021-22/+22
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* | Merge pull request #1846 from dh73/ast_feClaire Wolf2020-04-021-0/+3
|\ \ | |/ |/| Adding error message for when size (width) of number literal is zero
| * Replacing log_error for log_file_error due consistencyDiego H2020-03-311-2/+1
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| * Adding error message for when size (width) of number literal is zeroDiego H2020-03-301-0/+4
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* | verilog: Add location info for generate constructsDavid Shah2020-04-011-0/+6
|/ | | | Signed-off-by: David Shah <dave@ds0.me>
* Merge pull request #1811 from PeterCrozier/typedef_scopeN. Engelhardt2020-03-304-41/+81
|\ | | | | Support module/package/interface/block scope for typedef names.
| * Inline productions to follow house style.Peter Crozier2020-03-271-33/+29
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| * Error duplicate declarations of a typedef name in the same scope.Peter Crozier2020-03-242-3/+11
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| * Support module/package/interface/block scope for typedef names.Peter Crozier2020-03-234-20/+56
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* | Add support for SystemVerilog-style `define to Verilog frontendRupert Swarbrick2020-03-274-149/+578
|/ | | | | | | | | | | | | | | | | | | | | | | | | | | This patch should support things like `define foo(a, b = 3, c) a+b+c `foo(1, ,2) which will evaluate to 1+3+2. It also spots mistakes like `foo(1) (the 3rd argument doesn't have a default value, so a call site is required to set it). Most of the patch is a simple parser for the format in preproc.cc, but I've also taken the opportunity to wrap up the "name -> definition" map in a type, rather than use multiple std::map's. Since this type needs to be visible to code that touches defines, I've pulled it (and the frontend_verilog_preproc declaration) out into a new file at frontends/verilog/preproc.h and included that where necessary. Finally, the patch adds a few tests in tests/various to check that we are parsing everything correctly.
* Build pkg_user_types before parsing in case of changes in the design.Peter Crozier2020-03-221-6/+3
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* Clear pkg_user_types if no packages following a 'design -reset-vlog'.Peter2020-03-222-0/+5
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* Parser changes to support typedef.Peter2020-03-224-10/+88
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* Merge pull request #1787 from YosysHQ/mmicko/lexer_depsMiodrag Milanović2020-03-191-1/+1
|\ | | | | Add dependency to verilog_lexer.cc
| * Add one mode dependencyMiodrag Milanovic2020-03-191-1/+1
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* | Merge pull request #1775 from huaixv/asserts_locationsN. Engelhardt2020-03-191-7/+30
|\ \ | |/ |/| Add precise locations for asserts
| * Add precise locations for assertshuaixv2020-03-191-7/+30
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* | Add AST node source location information in a couple more parser rules.Alberto Gonzalez2020-03-171-0/+2
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* Merge pull request #1759 from zeldin/constant_with_comment_reduxMiodrag Milanović2020-03-142-19/+43
|\ | | | | refixed parsing of constant with comment between size and value
| * refixed parsing of constant with comment between size and valueMarcus Comstedt2020-03-112-19/+43
| | | | | | | | | | | | The three parts of a based constant (size, base, digits) are now three separate tokens, allowing the linear whitespace (including comments) between them to be treated as normal inter-token whitespace.
* | verilog: also set location for simple_behavioral_stmtEddie Hung2020-03-101-0/+4
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* | Set AST source locations in more parser rules.Alberto Gonzalez2020-03-101-2/+49
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* Fix partsel expr bit width handling and add test caseClaire Wolf2020-03-081-4/+6
| | | | Signed-off-by: Claire Wolf <claire@symbioticeda.com>
* Fix bison warning for "pure-parser" optionClaire Wolf2020-03-031-1/+1
| | | | Signed-off-by: Claire Wolf <claire@symbioticeda.com>
* Closes #1717. Add more precise Verilog source location information to AST ↵Alberto Gonzalez2020-02-234-32/+131
| | | | and RTLIL nodes.
* Merge pull request #1703 from YosysHQ/eddie/specify_improveEddie Hung2020-02-212-29/+81
|\ | | | | Improve specify parser
| * verilog: add support for more delays than just rise/fallEddie Hung2020-02-191-1/+40
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| * verilog: ignore ranges too without -specifyEddie Hung2020-02-131-1/+2
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| * verilog: improve specify support when not in -specify modeEddie Hung2020-02-131-13/+7
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| * verilog: ignore '&&&' when not in -specify modeEddie Hung2020-02-132-5/+6
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| * specify: system timing checks to accept min:typ:max tripleEddie Hung2020-02-131-12/+29
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* | Merge pull request #1642 from jjj11x/jjj11x/sv-enumClaire Wolf2020-02-201-2/+104
|\ \ | |/ |/| Enum support
| * add attributes for enumerated values in ilangJeff Wang2020-02-171-1/+8
| | | | | | | | | | | | - information also useful for strongly-typed enums (not implemented) - resolves enum values in ilang part of #1594 - still need to output enums to VCD (or better yet FST) files
| * lexer doesn't seem to return TOK_REG for logic anymoreJeff Wang2020-01-161-3/+4
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| * allow enum typedefsJeff Wang2020-01-161-1/+6
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| * partial rebase of PeterCrozier's enum work onto current masterJeff Wang2020-01-161-1/+90
| | | | | | | | | | | | | | | | | | | | | | I tried to keep only the enum-related changes, and minimize the diff. (The original commit also had a lot of work done to get typedefs working, but yosys has diverged quite a bit since the 2018-03-09 commit, with a new typedef implementation.) I did not include the import related changes either. Original commit: "Initial implementation of enum, typedef, import. Still a WIP." https://github.com/PeterCrozier/yosys/commit/881833aa738e7404987646ea8076284e911fce3f
* | Merge pull request #1679 from thasti/delay-parsingN. Engelhardt2020-02-131-2/+2
|\ \ | | | | | | Fix crash on wire declaration with delay
| * | correct wire declaration grammar for #1614Stefan Biereigel2020-02-031-2/+2
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* | sv: Improve handling of wildcard port connectionsDavid Shah2020-02-022-4/+6
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | hierarchy: Resolve SV wildcard port connectionsDavid Shah2020-02-021-1/+1
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | sv: Add lexing and parsing of .* (wildcard port conns)David Shah2020-02-022-1/+6
|/ | | | Signed-off-by: David Shah <dave@ds0.me>
* Fixed some missing "verilog_" in documentationRodrigo Alejandro Melo2019-12-132-2/+2
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* kernel: require \B_SIGNED=0 on $shl, $sshl, $shr, $sshr.whitequark2019-12-041-5/+5
| | | | | | | Before this commit, these cells would accept any \B_SIGNED and in case of \B_SIGNED=1, would still treat the \B input as unsigned. Also fix the Verilog frontend to never emit such constructs.
* sv: Correct parsing of always_comb, always_ff and always_latchDavid Shah2019-11-212-5/+40
| | | | Signed-off-by: David Shah <dave@ds0.me>
* Add check for valid macro names in macro definitionsClifford Wolf2019-11-071-7/+11
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add "verilog_defines -list" and "verilog_defines -reset"Clifford Wolf2019-10-211-0/+16
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Use "(id)" instead of "id" for types as temporary hackClifford Wolf2019-10-141-11/+69
|\ | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
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