| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | remove unnecessary blank line | Jeff Wang | 2020-02-17 | 1 | -2/+1 |
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| * | add attributes for enumerated values in ilang | Jeff Wang | 2020-02-17 | 3 | -2/+76 |
| | | | | | | | - information also useful for strongly-typed enums (not implemented) - resolves enum values in ilang part of #1594 - still need to output enums to VCD (or better yet FST) files | ||||
| * | separate out enum_item/param implementation when they should be different | Jeff Wang | 2020-02-17 | 1 | -7/+16 |
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| * | fix bug introduced by not taking all of PeterCrozier's changes in 16ea4ea6 | Jeff Wang | 2020-01-17 | 1 | -4/+6 |
| | | | | | | | | | The if(str == node->str) is in fact necessary (otherwise causes generate for in Multiplier_2D in tests/simple/multiplier.v to fail with error message "Right hand side of 3rd expression of generate for-loop is not constant!"). Note: in PeterCrozier's implementation, the break only breaks out of the switch-case, not the outer for loop. | ||||
| * | fix enum in generate blocks | Jeff Wang | 2020-01-16 | 1 | -0/+20 |
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| * | allow enums to be declared at toplevel scope | Jeff Wang | 2020-01-16 | 1 | -0/+7 |
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| * | lexer doesn't seem to return TOK_REG for logic anymore | Jeff Wang | 2020-01-16 | 1 | -3/+4 |
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| * | allow enum typedefs | Jeff Wang | 2020-01-16 | 1 | -1/+6 |
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| * | partial rebase of PeterCrozier's enum work onto current master | Jeff Wang | 2020-01-16 | 5 | -17/+207 |
| | | | | | | | | | | | | I tried to keep only the enum-related changes, and minimize the diff. (The original commit also had a lot of work done to get typedefs working, but yosys has diverged quite a bit since the 2018-03-09 commit, with a new typedef implementation.) I did not include the import related changes either. Original commit: "Initial implementation of enum, typedef, import. Still a WIP." https://github.com/PeterCrozier/yosys/commit/881833aa738e7404987646ea8076284e911fce3f | ||||
| * | read_aiger: $lut prefix in front | Eddie Hung | 2020-01-15 | 1 | -2/+2 |
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| * | read_aiger: also rename "$0" | Eddie Hung | 2020-01-14 | 1 | -2/+2 |
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| * | read_aiger: uniquify wires with $aiger<autoidx> prefix | Eddie Hung | 2020-01-13 | 2 | -9/+13 |
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| * | read_aiger: make $and/$not/$lut the prefix not suffix | Eddie Hung | 2020-01-13 | 1 | -5/+5 |
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| * | read_aiger: consistency between ascii and binary; also name latches | Eddie Hung | 2020-01-07 | 1 | -3/+9 |
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| * | read_aiger: connect identical signals together | Eddie Hung | 2020-01-07 | 1 | -0/+1 |
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| * | read_aiger: cope with latches and POs with same name | Eddie Hung | 2020-01-07 | 1 | -2/+12 |
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| * | read_aiger: default -clk_name to be empty | Eddie Hung | 2020-01-07 | 1 | -1/+1 |
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| * | parse_xaiger to not take box_lookup | Eddie Hung | 2019-12-31 | 2 | -18/+20 |
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| * | parse_xaiger to reorder ports too | Eddie Hung | 2019-12-31 | 1 | -41/+26 |
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| * | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-12-20 | 1 | -0/+16 |
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| | * | Merge pull request #1569 from YosysHQ/eddie/fix_1531 | Eddie Hung | 2019-12-19 | 1 | -0/+16 |
| | |\ | | | | | | | verilog: preserve size of $genval$-s in for loops | ||||
| | | * | Stray log_dump | Eddie Hung | 2019-12-11 | 1 | -1/+0 |
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| | | * | Preserve size of $genval$-s in for loops | Eddie Hung | 2019-12-11 | 1 | -0/+17 |
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| * | | | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-12-19 | 4 | -7/+28 |
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| | * | | Send people to symbioticeda.com instead of verific.com | Clifford Wolf | 2019-12-18 | 2 | -5/+26 |
| | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| | * | | Fixed some missing "verilog_" in documentation | Rodrigo Alejandro Melo | 2019-12-13 | 2 | -2/+2 |
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| * | | aiger frontend to user shorter, $-prefixed, names | Eddie Hung | 2019-12-17 | 1 | -14/+14 |
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| * | | Cleanup xaiger, remove unnecessary complexity with inout | Eddie Hung | 2019-12-17 | 1 | -23/+4 |
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| * | | read_xaiger to cope with optional '\n' after 'c' | Eddie Hung | 2019-12-17 | 1 | -2/+2 |
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| * | | Name inputs/outputs of aiger 'i%d' and 'o%d' | Eddie Hung | 2019-12-13 | 1 | -13/+6 |
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| * | | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-12-06 | 2 | -5/+9 |
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| | * | Merge pull request #1551 from whitequark/manual-cell-operands | Clifford Wolf | 2019-12-05 | 1 | -5/+5 |
| | |\ | | | | | | | Clarify semantics of comb cells, in particular shifts | ||||
| | | * | kernel: require \B_SIGNED=0 on $shl, $sshl, $shr, $sshr. | whitequark | 2019-12-04 | 1 | -5/+5 |
| | | | | | | | | | | | | | | | | | | | | | | Before this commit, these cells would accept any \B_SIGNED and in case of \B_SIGNED=1, would still treat the \B input as unsigned. Also fix the Verilog frontend to never emit such constructs. | ||||
| | * | | read_ilang: do bounds checking on bit indices | Marcin Kościelnicki | 2019-11-27 | 1 | -0/+4 |
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| * | | Call abc9 with "&write -n", and parse_xaiger() to cope | Eddie Hung | 2019-12-06 | 1 | -92/+85 |
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| * | | Do not connect undriven POs to 1'bx | Eddie Hung | 2019-12-06 | 1 | -8/+3 |
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| * | | Merge branch 'eddie/clkpart' into xaig_dff | Eddie Hung | 2019-11-22 | 5 | -18/+88 |
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| | * | Add Verific support for SVA nexttime properties | Clifford Wolf | 2019-11-22 | 1 | -0/+22 |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| | * | Improve handling of verific primitives in "verific -import -V" mode | Clifford Wolf | 2019-11-22 | 1 | -2/+2 |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| | * | Add Verific SVA support for "always" properties | Clifford Wolf | 2019-11-22 | 1 | -5/+15 |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| | * | sv: Correct parsing of always_comb, always_ff and always_latch | David Shah | 2019-11-21 | 2 | -5/+40 |
| | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
| | * | Correctly treat empty modules as blackboxes in Verific | Clifford Wolf | 2019-11-20 | 1 | -1/+1 |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| | * | Do not rename VHDL entities to "entity(impl)" when they are top modules | Clifford Wolf | 2019-11-20 | 2 | -5/+8 |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | | Consistent log message, ignore 's' extension | Eddie Hung | 2019-11-20 | 1 | -2/+3 |
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| * | | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-11-19 | 9 | -33/+260 |
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| | * | Add check for valid macro names in macro definitions | Clifford Wolf | 2019-11-07 | 1 | -7/+11 |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| | * | Improve naming scheme for (VHDL) modules imported from Verific | Clifford Wolf | 2019-10-24 | 1 | -3/+26 |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| | * | Add "verific -L" | Clifford Wolf | 2019-10-24 | 1 | -1/+12 |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| | * | Add "verilog_defines -list" and "verilog_defines -reset" | Clifford Wolf | 2019-10-21 | 1 | -0/+16 |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| | * | Fix handling of "restrict" in Verific front-end | Clifford Wolf | 2019-10-21 | 1 | -1/+1 |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
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