| Commit message (Collapse) | Author | Age | Files | Lines | ||
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| | | * | Added JSON upto and offset | Clifford Wolf | 2019-06-21 | 1 | -0/+12 | |
| | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | | * | Merge pull request #1119 from YosysHQ/eddie/fix1118 | Clifford Wolf | 2019-06-21 | 1 | -0/+1 | |
| | | |\ | | | | | | | | | Make genvar a signed type | |||||
| | | | * | Make genvar a signed type | Eddie Hung | 2019-06-20 | 1 | -0/+1 | |
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| | | * | | Maintain "is_unsized" state of constants | Eddie Hung | 2019-06-20 | 1 | -6/+6 | |
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| | * | | Reduce log_debug spam in parse_xaiger() | Eddie Hung | 2019-06-21 | 1 | -16/+19 | |
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| | * | | Workaround issues exposed by gcc-4.8 | Eddie Hung | 2019-06-21 | 1 | -0/+7 | |
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| | * | | Fix broken abc9.v test due to inout being 1'bx | Eddie Hung | 2019-06-20 | 1 | -3/+10 | |
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| | * | | Merge remote-tracking branch 'origin/master' into xaig | Eddie Hung | 2019-06-20 | 6 | -15/+77 | |
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| | | * | Merge branch 'unpacked_arrays' of https://github.com/towoe/yosys-sv into ↵ | Clifford Wolf | 2019-06-20 | 1 | -1/+7 | |
| | | |\ | | | | | | | | | | | | | towoe-unpacked_arrays | |||||
| | | | * | Unpacked array declaration using size | Tobias Wölfel | 2019-06-19 | 1 | -1/+7 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Allows fixed-sized array dimension specified by a single number. This commit is based on the work from PeterCrozier https://github.com/YosysHQ/yosys/pull/560. But is split out of the original work. | |||||
| | | * | | Add "read_verilog -pwires" feature, closes #1106 | Clifford Wolf | 2019-06-19 | 5 | -9/+44 | |
| | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | | * | | Add defaultvalue attribute | Clifford Wolf | 2019-06-19 | 1 | -0/+11 | |
| | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | | * | | Fix handling of "logic" variables with initial value | Clifford Wolf | 2019-06-19 | 1 | -2/+2 | |
| | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | | * | | Fixed brojen $error()/$info/$warning() on non-generate blocks | Udi Finkelstein | 2019-06-11 | 2 | -3/+13 | |
| | | |/ | | | | | | | | | | (within always/initial blocks) | |||||
| | * | | Fix issue with part of PI being 1'bx | Eddie Hung | 2019-06-20 | 1 | -4/+6 | |
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| | * | | Cleanup | Eddie Hung | 2019-06-16 | 1 | -20/+1 | |
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| * | | | Cleanup | Eddie Hung | 2019-06-16 | 1 | -23/+18 | |
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| * | | | Read init from outputs | Eddie Hung | 2019-06-15 | 1 | -0/+4 | |
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| * | | | Fix debug message | Eddie Hung | 2019-06-15 | 1 | -0/+1 | |
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| * | | | Fix log_debug messages | Eddie Hung | 2019-06-15 | 1 | -17/+23 | |
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| * | | | Missing close bracket | Eddie Hung | 2019-06-15 | 1 | -1/+1 | |
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| * | | | read_aiger to not require clk_name for latches, plus debug | Eddie Hung | 2019-06-15 | 1 | -21/+37 | |
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| * | | Cover __APPLE__ too for little to big endian | Eddie Hung | 2019-06-14 | 1 | -4/+7 | |
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| * | | Further cleanup based on @daveshah1 | Eddie Hung | 2019-06-14 | 1 | -10/+20 | |
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| * | | Resolve comments from @daveshah1 | Eddie Hung | 2019-06-14 | 1 | -2/+2 | |
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| * | | Cleanup | Eddie Hung | 2019-06-14 | 1 | -7/+3 | |
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| * | | Add TODO to parse_xaiger | Eddie Hung | 2019-06-14 | 1 | -0/+1 | |
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| * | | Optimise some more | Eddie Hung | 2019-06-13 | 1 | -58/+53 | |
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| * | | Move ConstEvalAig to aigerparse.cc | Eddie Hung | 2019-06-13 | 1 | -3/+161 | |
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| * | | Add ConstEvalAig specialised for AIGs | Eddie Hung | 2019-06-13 | 1 | -3/+2 | |
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| * | | parse_xaiger to cope with inouts | Eddie Hung | 2019-06-12 | 1 | -6/+0 | |
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| * | | Consistency | Eddie Hung | 2019-06-12 | 2 | -2/+2 | |
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| * | | Merge remote-tracking branch 'origin/master' into xaig | Eddie Hung | 2019-06-12 | 16 | -957/+1462 | |
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| | * | Fix spacing from spaces to tabs | Eddie Hung | 2019-06-07 | 1 | -362/+362 | |
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| | * | Fix spacing (entire file is wrong anyway, will fix later) | Eddie Hung | 2019-06-07 | 1 | -3/+3 | |
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| | * | Remove unnecessary std::getline() for ASCII | Eddie Hung | 2019-06-07 | 1 | -3/+0 | |
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| | * | Fix read_aiger -- create zero driver, fix init width, parse 'b' | Eddie Hung | 2019-06-07 | 2 | -13/+52 | |
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| | * | Fixes and cleanups in AST_TECALL handling | Clifford Wolf | 2019-06-07 | 3 | -46/+34 | |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | * | Merge branch 'pr_elab_sys_tasks' of https://github.com/udif/yosys into ↵ | Clifford Wolf | 2019-06-07 | 6 | -5/+64 | |
| | |\ | | | | | | | | | | clifford/pr983 | |||||
| | | * | Initial implementation of elaboration system tasks | Udi Finkelstein | 2019-05-03 | 6 | -5/+64 | |
| | | | | | | | | | | | | | | | | | | | | | | (IEEE1800-2017 section 20.11) This PR allows us to use $info/$warning/$error/$fatal **at elaboration time** within a generate block. This is very useful to stop a synthesis of a parametrized block when an illegal combination of parameters is chosen. | |||||
| | * | | Cleanup tux3-implicit_named_connection | Clifford Wolf | 2019-06-07 | 1 | -1/+1 | |
| | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | * | | Merge branch 'implicit_named_connection' of https://github.com/tux3/yosys ↵ | Clifford Wolf | 2019-06-07 | 1 | -1/+10 | |
| | |\ \ | | | | | | | | | | | | | into tux3-implicit_named_connection | |||||
| | | * | | SystemVerilog support for implicit named port connections | tux3 | 2019-06-06 | 1 | -9/+17 | |
| | | | | | | | | | | | | | | | | | | | | | This is the `foo foo(.port1, .port2);` SystemVerilog syntax introduced in IEEE1800-2005. | |||||
| | * | | | Merge pull request #1060 from antmicro/parsing_attr_on_port_conn | Clifford Wolf | 2019-06-06 | 1 | -10/+14 | |
| | |\ \ \ | | |/ / | |/| | | Added support for parsing attributes on port connections. | |||||
| | | * | | Fixed memory leak. | Maciej Kurc | 2019-06-05 | 1 | -0/+4 | |
| | | | | | | | | | | | | | | | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com> | |||||
| | | * | | Added support for parsing attributes on port connections. | Maciej Kurc | 2019-05-31 | 1 | -10/+10 | |
| | | | | | | | | | | | | | | | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com> | |||||
| | * | | | Only support Symbiotic EDA flavored Verific | Clifford Wolf | 2019-06-02 | 1 | -0/+8 | |
| | |/ / | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | * | | Enable Verific flag veri_elaborate_top_level_modules_having_interface_ports, ↵ | Clifford Wolf | 2019-05-30 | 1 | -0/+3 | |
| | | | | | | | | | | | | | | | | | | | fixes #1055 Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | * | | Merge branch 'master' into wandwor | Stefan Biereigel | 2019-05-27 | 5 | -14/+47 | |
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| | | * \ | Merge pull request #1044 from mmicko/invalid_width_range | Clifford Wolf | 2019-05-27 | 1 | -1/+2 | |
| | | |\ \ | | | | | | | | | | | Give error instead of asserting for invalid range, fixes #947 | |||||
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