| Commit message (Collapse) | Author | Age | Files | Lines | ||
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| * | | | read_aiger: more accurate debug message | Eddie Hung | 2020-01-09 | 1 | -2/+4 | |
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| * | | | read_aiger: do not double-count outputs for flops | Eddie Hung | 2020-01-09 | 1 | -6/+0 | |
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| * | | | Merge remote-tracking branch 'origin/master' into eddie/abc9_refactor | Eddie Hung | 2020-01-07 | 1 | -5/+20 | |
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| | * | | read_aiger: consistency between ascii and binary; also name latches | Eddie Hung | 2020-01-07 | 1 | -3/+9 | |
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| | * | | read_aiger: connect identical signals together | Eddie Hung | 2020-01-07 | 1 | -0/+1 | |
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| | * | | read_aiger: cope with latches and POs with same name | Eddie Hung | 2020-01-07 | 1 | -2/+12 | |
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| | * | | read_aiger: default -clk_name to be empty | Eddie Hung | 2020-01-07 | 1 | -1/+1 | |
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| * | | | read_aiger fixes | Eddie Hung | 2020-01-07 | 1 | -5/+5 | |
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| * | | | read_aiger: do not process box connections, work standalone | Eddie Hung | 2020-01-07 | 1 | -115/+46 | |
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| * | | | read_aiger: consistency between ascii and binary | Eddie Hung | 2020-01-07 | 1 | -13/+7 | |
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| * | | | read_aiger: add -xaiger option | Eddie Hung | 2020-01-06 | 1 | -7/+17 | |
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| * | | parse_xaiger to not take box_lookup | Eddie Hung | 2019-12-31 | 2 | -18/+20 | |
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| * | | parse_xaiger to reorder ports too | Eddie Hung | 2019-12-31 | 1 | -41/+26 | |
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| * | | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-12-20 | 1 | -0/+16 | |
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| | * \ | Merge pull request #1569 from YosysHQ/eddie/fix_1531 | Eddie Hung | 2019-12-19 | 1 | -0/+16 | |
| | |\ \ | | | | | | | | | verilog: preserve size of $genval$-s in for loops | |||||
| | | * | | Stray log_dump | Eddie Hung | 2019-12-11 | 1 | -1/+0 | |
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| | | * | | Preserve size of $genval$-s in for loops | Eddie Hung | 2019-12-11 | 1 | -0/+17 | |
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| * | | | | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-12-19 | 4 | -7/+28 | |
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| | * | | | Send people to symbioticeda.com instead of verific.com | Clifford Wolf | 2019-12-18 | 2 | -5/+26 | |
| | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | * | | | Fixed some missing "verilog_" in documentation | Rodrigo Alejandro Melo | 2019-12-13 | 2 | -2/+2 | |
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| * | | | aiger frontend to user shorter, $-prefixed, names | Eddie Hung | 2019-12-17 | 1 | -14/+14 | |
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| * | | | Cleanup xaiger, remove unnecessary complexity with inout | Eddie Hung | 2019-12-17 | 1 | -23/+4 | |
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| * | | | read_xaiger to cope with optional '\n' after 'c' | Eddie Hung | 2019-12-17 | 1 | -2/+2 | |
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| * | | | Name inputs/outputs of aiger 'i%d' and 'o%d' | Eddie Hung | 2019-12-13 | 1 | -13/+6 | |
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| * | | | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-12-06 | 2 | -5/+9 | |
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| | * | | Merge pull request #1551 from whitequark/manual-cell-operands | Clifford Wolf | 2019-12-05 | 1 | -5/+5 | |
| | |\ \ | | | | | | | | | Clarify semantics of comb cells, in particular shifts | |||||
| | | * | | kernel: require \B_SIGNED=0 on $shl, $sshl, $shr, $sshr. | whitequark | 2019-12-04 | 1 | -5/+5 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Before this commit, these cells would accept any \B_SIGNED and in case of \B_SIGNED=1, would still treat the \B input as unsigned. Also fix the Verilog frontend to never emit such constructs. | |||||
| | * | | | read_ilang: do bounds checking on bit indices | Marcin Kościelnicki | 2019-11-27 | 1 | -0/+4 | |
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| * | | | Call abc9 with "&write -n", and parse_xaiger() to cope | Eddie Hung | 2019-12-06 | 1 | -92/+85 | |
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| * | | | Do not connect undriven POs to 1'bx | Eddie Hung | 2019-12-06 | 1 | -8/+3 | |
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| * | | | Merge branch 'eddie/clkpart' into xaig_dff | Eddie Hung | 2019-11-22 | 5 | -18/+88 | |
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| | * | | Add Verific support for SVA nexttime properties | Clifford Wolf | 2019-11-22 | 1 | -0/+22 | |
| | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | * | | Improve handling of verific primitives in "verific -import -V" mode | Clifford Wolf | 2019-11-22 | 1 | -2/+2 | |
| | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | * | | Add Verific SVA support for "always" properties | Clifford Wolf | 2019-11-22 | 1 | -5/+15 | |
| | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | * | | sv: Correct parsing of always_comb, always_ff and always_latch | David Shah | 2019-11-21 | 2 | -5/+40 | |
| | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | |||||
| | * | | Correctly treat empty modules as blackboxes in Verific | Clifford Wolf | 2019-11-20 | 1 | -1/+1 | |
| | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | * | | Do not rename VHDL entities to "entity(impl)" when they are top modules | Clifford Wolf | 2019-11-20 | 2 | -5/+8 | |
| | |/ | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | Consistent log message, ignore 's' extension | Eddie Hung | 2019-11-20 | 1 | -2/+3 | |
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| * | | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-11-19 | 9 | -33/+260 | |
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| | * | Add check for valid macro names in macro definitions | Clifford Wolf | 2019-11-07 | 1 | -7/+11 | |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | * | Improve naming scheme for (VHDL) modules imported from Verific | Clifford Wolf | 2019-10-24 | 1 | -3/+26 | |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | * | Add "verific -L" | Clifford Wolf | 2019-10-24 | 1 | -1/+12 | |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | * | Add "verilog_defines -list" and "verilog_defines -reset" | Clifford Wolf | 2019-10-21 | 1 | -0/+16 | |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | * | Fix handling of "restrict" in Verific front-end | Clifford Wolf | 2019-10-21 | 1 | -1/+1 | |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | * | Fix parsing of .cname BLIF statements | Clifford Wolf | 2019-10-16 | 1 | -1/+1 | |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | * | Add .blackbox support to blif front-end | Clifford Wolf | 2019-10-16 | 1 | -0/+6 | |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | * | Use "(id)" instead of "id" for types as temporary hack | Clifford Wolf | 2019-10-14 | 5 | -20/+187 | |
| | |\ | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | | * | frontends/ast: code style | David Shah | 2019-10-03 | 1 | -2/+1 | |
| | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | |||||
| | | * | sv: Fix typedefs in blocks | David Shah | 2019-10-03 | 1 | -2/+2 | |
| | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | |||||
| | | * | sv: Disambiguate interface ports | David Shah | 2019-10-03 | 1 | -3/+19 | |
| | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | |||||
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index : iCE40/yosys | |
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