iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Added $assume cell type	Clifford Wolf	2015-02-26	1	-0/+7
*	Added $meminit support to "memory" command	Clifford Wolf	2015-02-14	1	-0/+1
*	Added $meminit cell type	Clifford Wolf	2015-02-14	1	-0/+9
*	Added SigSpec::has_const()	Clifford Wolf	2015-02-08	1	-0/+12
*	Added cell->known(), cell->input(portname), cell->output(portname)	Clifford Wolf	2015-02-07	1	-0/+34
*	Skip blackbox modules in design->selected_modules()	Clifford Wolf	2015-02-03	1	-3/+5
*	Added "equiv_make -blacklist <file> -encfile <file>"	Clifford Wolf	2015-01-31	1	-0/+15
*	Added dict/pool.sort()	Clifford Wolf	2015-01-24	1	-0/+30
*	Progress in equiv_simple	Clifford Wolf	2015-01-21	1	-2/+5
*	Added equiv_make command	Clifford Wolf	2015-01-19	1	-0/+9
*	Added $equiv cell type	Clifford Wolf	2015-01-19	1	-0/+8
*	Optimizing no-op cell->setPort()	Clifford Wolf	2015-01-17	1	-1/+3
*	Removed SigSpec::extend_xx() api	Clifford Wolf	2015-01-01	1	-18/+0
*	added hashlib::mkhash_init	Clifford Wolf	2014-12-30	1	-1/+1
*	Added "yosys -X"	Clifford Wolf	2014-12-29	1	-0/+37
*	Added mkhash_xorshift()	Clifford Wolf	2014-12-29	1	-10/+15
*	Added memhasher (yosys -M)	Clifford Wolf	2014-12-28	1	-0/+3
*	Fixed performance bug in object hashing	Clifford Wolf	2014-12-28	1	-5/+5
*	Renamed hashmap.h to hashlib.h, some related improvements	Clifford Wolf	2014-12-28	1	-2/+16
*	More dict/pool related changes	Clifford Wolf	2014-12-27	1	-9/+7
*	More hashtable finetuning	Clifford Wolf	2014-12-27	1	-2/+2
*	Replaced std::unordered_set (nodict) with Yosys::pool	Clifford Wolf	2014-12-26	1	-15/+15
*	Replaced std::unordered_map as implementation for Yosys::dict	Clifford Wolf	2014-12-26	1	-11/+11
*	Added new_dict (hashmap.h) and re-enabled code coverage counters	Clifford Wolf	2014-12-26	1	-1/+1
*	Added Yosys::{dict,nodict,vector} container types	Clifford Wolf	2014-12-26	1	-23/+77
*	Renamed extend() to extend_xx(), changed most users to extend_u0()	Clifford Wolf	2014-12-24	1	-8/+7
*	Added IdString::destruct_guard hack	Clifford Wolf	2014-12-11	1	-0/+1
*	Added bool constructors to SigBit and SigSpec	Clifford Wolf	2014-12-08	1	-0/+10
*	Added module->addDffe() and module->addDffeGate()	Clifford Wolf	2014-12-08	1	-1/+24
*	Added $dffe cell type	Clifford Wolf	2014-12-08	1	-0/+11
*	Added $_DFFE_??_ cell types	Clifford Wolf	2014-12-08	1	-0/+5
*	Added log_warning() API	Clifford Wolf	2014-11-09	1	-3/+3
*	Added support for $readmemh/$readmemb	Clifford Wolf	2014-10-26	1	-1/+1
*	Fixed various VS warnings	Clifford Wolf	2014-10-18	1	-2/+2
*	Various win32 / vs build fixes	Clifford Wolf	2014-10-17	1	-1/+1
*	Fixed RTLIL::SigSpec::parse() for out-of-range bit- and part-selects	Clifford Wolf	2014-10-16	1	-1/+8
*	Renamed SIZE() to GetSize() because of name collision on Win32	Clifford Wolf	2014-10-10	1	-29/+29
*	Added $_BUF_ cell type	Clifford Wolf	2014-10-03	1	-0/+1
*	Initialize RTLIL::Const from std::vector<bool>	Clifford Wolf	2014-09-19	1	-0/+7
*	Fixed monitor notifications for removed cell	Clifford Wolf	2014-09-14	1	-0/+3
*	Added $lcu cell type	Clifford Wolf	2014-09-08	1	-0/+14
*	Added "$fa" cell type	Clifford Wolf	2014-09-08	1	-0/+15
*	Added $macc cell type	Clifford Wolf	2014-09-06	1	-1/+13
*	Removed $bu0 cell type	Clifford Wolf	2014-09-04	1	-2/+1
*	Create a default selection stack in RTLIL::Design::Design()	Clifford Wolf	2014-09-02	1	-0/+1
*	Using std::vector<RTLIL::State> instead of RTLIL::Const for RTLIL::SigChunk::...	Clifford Wolf	2014-09-01	1	-33/+29
*	Added $lut support in test_cell, techmap, satgen	Clifford Wolf	2014-08-31	1	-3/+7
*	Added design->scratchpad	Clifford Wolf	2014-08-30	1	-0/+61
*	Added $alu cell type	Clifford Wolf	2014-08-30	1	-0/+14
*	Fixed module->addPmux()	Clifford Wolf	2014-08-30	1	-1/+0