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rtlil.cc
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Author
Age
Files
Lines
*
Fixed a typo in RTLIL::Module::addReduce...
Clifford Wolf
2014-03-10
1
-5
/
+5
*
Added RTLIL::Module::add... helper methods
Clifford Wolf
2014-03-10
1
-0
/
+236
*
Improved checking of internal cell conventions
Clifford Wolf
2014-02-08
1
-8
/
+17
*
Added $slice and $concat cell types
Clifford Wolf
2014-02-07
1
-0
/
+18
*
Stronger checking of internal cells
Clifford Wolf
2014-02-07
1
-29
/
+37
*
Added generic RTLIL::SigSpec::parse_sel() with support for selection variables
Clifford Wolf
2014-02-06
1
-0
/
+18
*
Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem)
Clifford Wolf
2014-02-03
1
-0
/
+2
*
Added RTLIL::SigSpec::to_single_sigbit()
Clifford Wolf
2014-02-02
1
-0
/
+9
*
Added $assert cell
Clifford Wolf
2014-01-19
1
-0
/
+7
*
Added RTLIL::SigSpec::optimized() API
Clifford Wolf
2014-01-03
1
-0
/
+7
*
Added correct handling of $memwr priority
Clifford Wolf
2014-01-03
1
-0
/
+1
*
Added additional checks for A_SIGNED == B_SIGNED for cells with that constraint
Clifford Wolf
2013-12-31
1
-4
/
+11
*
Added $bu0 cell (for easy correct $eq/$ne mapping)
Clifford Wolf
2013-12-28
1
-1
/
+1
*
Added support for non-const === and !== (for miter circuits)
Clifford Wolf
2013-12-27
1
-1
/
+1
*
Fixes and improvements in RTLIL::SigSpec::parse
Clifford Wolf
2013-12-07
1
-2
/
+12
*
Replaced signed_parameters API with CONST_FLAG_SIGNED
Clifford Wolf
2013-12-04
1
-1
/
+1
*
Replaced RTLIL::Const::str with generic decoder method
Clifford Wolf
2013-12-04
1
-5
/
+27
*
Remove auto_wire framework (smarter than the verilog standard)
Clifford Wolf
2013-11-24
1
-6
/
+0
*
Implemented correct handling of signed module parameters
Clifford Wolf
2013-11-24
1
-1
/
+1
*
Massive performance improvement from refactoring RTLIL::SigSpec::optimize()
Clifford Wolf
2013-11-22
1
-30
/
+13
*
Added SigBit struct and refactored RTLIL::SigSpec::extract
Clifford Wolf
2013-11-22
1
-24
/
+85
*
Added information on all internal cell types to internal checker
Clifford Wolf
2013-11-11
1
-0
/
+340
*
Improved user-friendliness of "sat" and "eval" expression parsing
Clifford Wolf
2013-11-09
1
-0
/
+14
*
Renamed extend_un0() to extend_u0() and use it in genrtlil
Clifford Wolf
2013-11-07
1
-1
/
+1
*
Fixed type of sign extension in opt_const $eq/$ne handling
Clifford Wolf
2013-11-07
1
-0
/
+16
*
Added eval -vloghammer_report mode
Clifford Wolf
2013-11-06
1
-0
/
+3
*
Changed NEW_WIRE API to return the wire, not the signal
Clifford Wolf
2013-10-18
1
-1
/
+1
*
Added RTLIL NEW_WIRE macro
Clifford Wolf
2013-10-18
1
-0
/
+9
*
Added "design" command (-reset, -save, -load)
Clifford Wolf
2013-07-27
1
-0
/
+89
*
Added "eval" pass
Clifford Wolf
2013-06-19
1
-0
/
+85
*
Added RTLIL::Module::fixup_ports() API and RTLIL::*::rewrite_sigspecs() API
Clifford Wolf
2013-06-18
1
-2
/
+31
*
Added "dump" command (part ilang backend)
Clifford Wolf
2013-06-02
1
-7
/
+7
*
Improved opt_share for reduce cells
Clifford Wolf
2013-03-29
1
-3
/
+10
*
Create nice errors when calling RTLIL::Module::derive() of base class
Clifford Wolf
2013-03-26
1
-3
/
+3
*
initial import
Clifford Wolf
2013-01-05
1
-0
/
+1081