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* Added RTLIL::SigSpec::remove_const() handling of packed SigSpecsClifford Wolf2014-07-271-9/+26
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* Added RTLIL::Module::wire(id) and cell(id) lookup functionsClifford Wolf2014-07-271-0/+12
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* Refactoring: Renamed RTLIL::Design::modules to modules_Clifford Wolf2014-07-271-9/+9
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* Added RTLIL::ObjIterator and RTLIL::ObjRangeClifford Wolf2014-07-271-6/+23
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* Refactoring: Renamed RTLIL::Module::cells to cells_Clifford Wolf2014-07-271-12/+12
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* Refactoring: Renamed RTLIL::Module::wires to wires_Clifford Wolf2014-07-271-20/+20
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* Changed more code to the new RTLIL::Wire constructorsClifford Wolf2014-07-261-1/+13
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* Changed a lot of code to the new RTLIL::Wire constructorsClifford Wolf2014-07-261-0/+40
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* Added RTLIL::Cell::has(portname)Clifford Wolf2014-07-261-4/+9
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* Manual fixes for new cell connections APIClifford Wolf2014-07-261-11/+11
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* Changed users of cell->connections_ to the new API (sed command)Clifford Wolf2014-07-261-82/+82
| | | | | | | | | git grep -l 'connections_' | xargs sed -i -r -e ' s/(->|\.)connections_\["([^"]*)"\] = (.*);/\1set("\2", \3);/g; s/(->|\.)connections_\["([^"]*)"\]/\1get("\2")/g; s/(->|\.)connections_.at\("([^"]*)"\)/\1get("\2")/g; s/(->|\.)connections_.push_back/\1connect/g; s/(->|\.)connections_/\1connections()/g;'
* Added some missing "const" in rtlil.hClifford Wolf2014-07-261-5/+5
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* Added RTLIL::Module::connections()Clifford Wolf2014-07-261-0/+5
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* Added RTLIL::Module::connect(const RTLIL::SigSig&)Clifford Wolf2014-07-261-0/+5
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* Automatically pack SigSpec on copy/assignClifford Wolf2014-07-261-17/+60
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* Added new RTLIL::Cell port access methodsClifford Wolf2014-07-261-0/+63
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* Renamed RTLIL::{Module,Cell}::connections to connections_Clifford Wolf2014-07-261-83/+88
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* Added copy-constructor-like module->addCell(name, other) methodClifford Wolf2014-07-261-8/+11
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* Use only module->addCell() and module->remove() to create and delete cellsClifford Wolf2014-07-251-2/+35
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* Added RTLIL::SigSpec is_chunk()/as_chunk() APIClifford Wolf2014-07-251-0/+17
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* Fixed typo in cover idClifford Wolf2014-07-251-1/+1
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* Replaced more old SigChunk programming patternsClifford Wolf2014-07-241-0/+17
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* Some improvements in SigSpec packing/unpacking and checkingClifford Wolf2014-07-241-8/+29
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* Small changes regarding cover() and check() in SigSpecClifford Wolf2014-07-241-10/+5
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* Added support for YOSYS_COVER_FILE env variableClifford Wolf2014-07-241-0/+2
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* Added cover() calls to RTLIL::SigSpec methodsClifford Wolf2014-07-241-5/+93
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* Added hashing to RTLIL::SigSpec relational and equal operatorsClifford Wolf2014-07-231-15/+64
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* Disabled RTLIL::SigSpec::check() in release buildsClifford Wolf2014-07-231-0/+2
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* Fixed release buildClifford Wolf2014-07-231-0/+2
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* Added RTLIL::SigSpec::repeat()Clifford Wolf2014-07-231-0/+8
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* Removed RTLIL::SigSpec::optimize()Clifford Wolf2014-07-231-105/+9
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* Turned RTLIL::SigSpec::optimize() to a no-op: a packed SigSpec is now always ↵Clifford Wolf2014-07-231-7/+42
| | | | optimized
* Removed RTLIL::SigSpec::expand() methodClifford Wolf2014-07-231-41/+0
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* Replaced RTLIL::SigSpec::operator!=() with inline versionClifford Wolf2014-07-231-7/+0
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* Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3Clifford Wolf2014-07-231-14/+10
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* Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3Clifford Wolf2014-07-231-16/+2
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* Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 1/3Clifford Wolf2014-07-231-0/+32
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* Some cleanups in RTLIL::SigChunk::SigChunk(const RTLIL::Const&)Clifford Wolf2014-07-231-4/+4
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* SigSpec refactoring: More cleanups of old SigSpec use patternClifford Wolf2014-07-221-1/+11
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* SigSpec refactoring: rewrote some RTLIL::SigSpec methods to use unpacked formClifford Wolf2014-07-221-182/+113
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* Removed RTLIL::SigChunk::compare()Clifford Wolf2014-07-221-24/+5
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* SigSpec refactoring: added RTLIL::SigSpec::bits() and pack/unpack apiClifford Wolf2014-07-221-8/+103
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* SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, ↵Clifford Wolf2014-07-221-1/+1
| | | | created interim RTLIL::SigSpec::chunks_rw()
* SigSpec refactoring: using the accessor functions everywhereClifford Wolf2014-07-221-44/+44
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* SigSpec refactoring: renamed the SigSpec members to chunks_ and width_ and ↵Clifford Wolf2014-07-221-149/+149
| | | | added accessor functions
* SigSpec refactoring: renamed chunks and width to __chunks and __widthClifford Wolf2014-07-221-193/+193
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* Removed deprecated module->new_wire()Clifford Wolf2014-07-211-15/+6
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* Added module->remove(), module->addWire(), module->addCell(), cell->check()Clifford Wolf2014-07-211-8/+39
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* Added std::set<RTLIL::SigBit> to RTLIL::SigSpec conversionClifford Wolf2014-07-201-3/+10
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* Added function-like cell creation helpersClifford Wolf2014-07-181-73/+103
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