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* kernel: Use constids.inc for global/constant IdStringsEddie Hung2020-04-021-6/+4
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* Merge pull request #1845 from YosysHQ/eddie/kernel_speedupEddie Hung2020-04-021-288/+244
|\ | | | | kernel: speedup by using more pass-by-const-ref
| * kernel: pass-by-value into Design::scratchpad_set_string() tooEddie Hung2020-03-271-2/+2
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| * kernel: Cell::set{Port,Param}() to pass by value, but use std::moveEddie Hung2020-03-261-5/+5
| | | | | | | | Otherwise cell->setPort(ID::A, cell->getPort(ID::B)) could be invalid
| * kernel: SigSpec copies to not trigger pack()Eddie Hung2020-03-181-33/+4
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| * kernel: more pass by const ref, more speedupsEddie Hung2020-03-181-180/+174
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| * kernel: speedupEddie Hung2020-03-181-30/+23
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| * kernel: fix DeleteWireWorkerEddie Hung2020-03-171-9/+4
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| * kernel: SigSpec use more const& + overloads to prevent implicit SigSpecEddie Hung2020-03-131-31/+39
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| * kernel: optimise Module::remove(const pool<RTLIL::Wire*>()Eddie Hung2020-03-121-10/+5
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* | Add support for SystemVerilog-style `define to Verilog frontendRupert Swarbrick2020-03-271-0/+2
|/ | | | | | | | | | | | | | | | | | | | | | | | | | | This patch should support things like `define foo(a, b = 3, c) a+b+c `foo(1, ,2) which will evaluate to 1+3+2. It also spots mistakes like `foo(1) (the 3rd argument doesn't have a default value, so a call site is required to set it). Most of the patch is a simple parser for the format in preproc.cc, but I've also taken the opportunity to wrap up the "name -> definition" map in a type, rather than use multiple std::map's. Since this type needs to be visible to code that touches defines, I've pulled it (and the frontend_verilog_preproc declaration) out into a new file at frontends/verilog/preproc.h and included that where necessary. Finally, the patch adds a few tests in tests/various to check that we are parsing everything correctly.
* Closes #1717. Add more precise Verilog source location information to AST ↵Alberto Gonzalez2020-02-231-2/+0
| | | | and RTLIL nodes.
* specify: system timing checks to accept min:typ:max tripleEddie Hung2020-02-131-2/+6
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* Add RTLIL::constpad, init by yosys_setup(); use for abc9Eddie Hung2020-01-081-0/+1
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* Always create $shl, $shr, $sshl, $sshr cells with unsigned B inputsClifford Wolf2020-01-021-4/+25
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* kernel: require \B_SIGNED=0 on $shl, $sshl, $shr, $sshr.whitequark2019-12-041-3/+21
| | | | | | | Before this commit, these cells would accept any \B_SIGNED and in case of \B_SIGNED=1, would still treat the \B input as unsigned. Also fix the Verilog frontend to never emit such constructs.
* Fix for SigSpec() == SigSpec(State::Sx, 0) to be true againEddie Hung2019-10-041-0/+6
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* Fix typoEddie Hung2019-09-301-1/+1
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* Avoid work in replace() if rules empty.Henner Zeller2019-09-291-0/+2
| | | | | | | This speeds up processing when number of bits are large but there is actually nothing to replace. Adresses part of #1382. Signed-off-by: Henner Zeller <h.zeller@acm.org>
* Use more ID::{A,B,Y,blackbox,whitebox}Eddie Hung2019-08-151-96/+96
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* Add YOSYS_NO_IDS_REFCNT configuration macroClifford Wolf2019-08-111-1/+3
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Use ID() in kernel/*, add simple ID:: hack (to be improved upon later)Clifford Wolf2019-08-111-578/+585
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* More improvements and cleanups in IdString subsystemClifford Wolf2019-08-111-0/+2
| | | | | | | | | - better use of "inline" keyword - deprecate "sticky" IDs feature - improve handling of empty ID - add move constructor Signed-off-by: Clifford Wolf <clifford@clifford.at>
* RTLIL::S{0,1} -> State::S{0,1}Eddie Hung2019-08-071-6/+6
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* stoi -> atoiEddie Hung2019-08-071-3/+3
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* Fix typosEddie Hung2019-08-061-2/+2
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* Use std::stoi instead of atoi(<str>.c_str())Eddie Hung2019-08-061-3/+3
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* Use IdString::begins_with()Eddie Hung2019-08-061-4/+4
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* Make liberal use of IdString.in()Eddie Hung2019-08-061-1/+1
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* Add $_NMUX_, add "abc -g cmos", add proper cmos cell costsClifford Wolf2019-08-061-0/+2
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* In RTLIL::Module::check(), check process invariants.whitequark2019-06-191-1/+28
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* Add rewrite_sigspecs2, Improve remove() wiresClifford Wolf2019-05-151-7/+22
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Minor optimization to get_attribute_boolMatthew Daiter2019-05-071-4/+8
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* Merge remote-tracking branch 'origin/master' into clifford/specifyEddie Hung2019-05-031-1/+1
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| * Fix performance bug in RTLIL::SigSpec::operator==(), fixes #970Clifford Wolf2019-04-301-1/+1
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Improve $specrule interfaceClifford Wolf2019-04-231-2/+2
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Improve $specrule interfaceClifford Wolf2019-04-231-1/+2
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Add $specrule cells for $setup/$hold/$skew specify rulesClifford Wolf2019-04-231-0/+15
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Rename T_{RISE,FALL}_AVG to T_{RISE,FALL}_TYP to better match verilog std ↵Clifford Wolf2019-04-231-2/+2
| | | | | | | | | | | | nomenclature Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Add InternalCellChecker support for $specify2 and $specify3Clifford Wolf2019-04-231-7/+21
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Add specify parserClifford Wolf2019-04-231-0/+10
|/ | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Merge pull request #905 from christian-krieg/feature/python_bindingsClifford Wolf2019-04-221-1/+97
|\ | | | | Feature/python bindings
| * Global lists in rtlil.cc are now static objectsBenedikt Tutzer2019-04-031-10/+10
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| * Merge remote-tracking branch 'origin/master' into feature/python_bindingsBenedikt Tutzer2019-03-281-3/+31
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| * | added some checks if python is enabled to make sure everything compiles if ↵Benedikt Tutzer2018-08-201-4/+2
| | | | | | | | | | | | python is disabled in the makefile
| * | Added Wrappers for:Benedikt Tutzer2018-08-131-1/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | -IdString -Const -CaseRule -SwitchRule -SyncRule -Process -SigChunk -SigBit -SigSpec With all their member functions as well as the remaining member functions for Cell, Wire, Module and Design and static functions of rtlil.h
| * | added destructors for wires and cellsBenedikt Tutzer2018-07-101-0/+14
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| * | removed debug outputBenedikt Tutzer2018-07-091-1/+0
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| * | multiple designs can now exist independent from each other. ↵Benedikt Tutzer2018-07-091-0/+55
| | | | | | | | | | | | Cells/Wires/Modules can now move to a different parent without referencing issues
* | | Add "wbflip" commandClifford Wolf2019-04-201-2/+5
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
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