iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Some cleanups in "clean"	Clifford Wolf	2015-02-24	1	-0/+8
*	Added SigSpec::has_const()	Clifford Wolf	2015-02-08	1	-0/+1
*	Added cell->known(), cell->input(portname), cell->output(portname)	Clifford Wolf	2015-02-07	1	-0/+5
*	Added "equiv_make -blacklist <file> -encfile <file>"	Clifford Wolf	2015-01-31	1	-0/+1
*	Synced RTLIL::unescape_id() to log_id() behavior	Clifford Wolf	2015-01-30	1	-3/+9
*	Added dict/pool.sort()	Clifford Wolf	2015-01-24	1	-0/+4
*	Added equiv_make command	Clifford Wolf	2015-01-19	1	-1/+2
*	Removed SigSpec::extend_xx() api	Clifford Wolf	2015-01-01	1	-1/+0
*	Progress in memory_bram	Clifford Wolf	2014-12-31	1	-5/+5
*	IdString optimization	Clifford Wolf	2014-12-31	1	-0/+6
*	added hashlib::mkhash_init	Clifford Wolf	2014-12-30	1	-1/+1
*	Added "yosys -X"	Clifford Wolf	2014-12-29	1	-0/+11
*	Converting "share" to dict<> and pool<> complete	Clifford Wolf	2014-12-29	1	-2/+9
*	Added mkhash_xorshift()	Clifford Wolf	2014-12-29	1	-2/+3
*	Fixed performance bug in object hashing	Clifford Wolf	2014-12-28	1	-1/+1
*	Renamed hashmap.h to hashlib.h, some related improvements	Clifford Wolf	2014-12-28	1	-5/+26
*	More dict/pool related changes	Clifford Wolf	2014-12-27	1	-2/+2
*	More hashtable finetuning	Clifford Wolf	2014-12-27	1	-3/+5
*	Replaced std::unordered_set (nodict) with Yosys::pool	Clifford Wolf	2014-12-26	1	-113/+19
*	Replaced std::unordered_map as implementation for Yosys::dict	Clifford Wolf	2014-12-26	1	-2/+30
*	Added Yosys::{dict,nodict,vector} container types	Clifford Wolf	2014-12-26	1	-263/+357
*	Renamed extend() to extend_xx(), changed most users to extend_u0()	Clifford Wolf	2014-12-24	1	-1/+1
*	Added support for multiple clock domains to "abc" pass	Clifford Wolf	2014-12-21	1	-0/+1
*	Fixed build with gcc 4.6	Clifford Wolf	2014-12-16	1	-1/+1
*	Added IdString::destruct_guard hack	Clifford Wolf	2014-12-11	1	-0/+13
*	Added bool constructors to SigBit and SigSpec	Clifford Wolf	2014-12-08	1	-0/+2
*	Added module->addDffe() and module->addDffeGate()	Clifford Wolf	2014-12-08	1	-0/+2
*	Improved TopoSort determinism	Clifford Wolf	2014-11-07	1	-1/+1
*	Fixed a few VS warnings	Clifford Wolf	2014-10-17	1	-1/+1
*	Made iterators extend std::iterator and added == operator	William Speirs	2014-10-15	1	-2/+4
*	Added support for "keep" on modules	Clifford Wolf	2014-09-29	1	-0/+5
*	Initialize RTLIL::Const from std::vector<bool>	Clifford Wolf	2014-09-19	1	-1/+2
*	Removed $bu0 cell type	Clifford Wolf	2014-09-04	1	-2/+0
*	Using std::vector<RTLIL::State> instead of RTLIL::Const for RTLIL::SigChunk::...	Clifford Wolf	2014-09-01	1	-3/+3
*	Added RTLIL::Const::size()	Clifford Wolf	2014-08-31	1	-0/+2
*	Typo fixes in cell->*Param() API	Clifford Wolf	2014-08-31	1	-4/+4
*	Added design->scratchpad	Clifford Wolf	2014-08-30	1	-0/+11
*	Added is_signed argument to SigSpec.as_int() and Const.as_int()	Clifford Wolf	2014-08-24	1	-2/+2
*	Added emscripten (emcc) support to build system and some build fixes	Clifford Wolf	2014-08-22	1	-3/+2
*	Added mod->addGate() methods for new gate types	Clifford Wolf	2014-08-19	1	-10/+24
*	Added module->uniquify()	Clifford Wolf	2014-08-16	1	-0/+3
*	Renamed $_INV_ cell type to $_NOT_	Clifford Wolf	2014-08-15	1	-2/+2
*	More idstring sort_by_* helpers and fixed tpl ordering in techmap	Clifford Wolf	2014-08-15	1	-1/+13
*	Added RTLIL::SigSpec::to_sigbit_map()	Clifford Wolf	2014-08-14	1	-0/+1
*	Added sig.{replace,remove,extract} variants for std::{map,set} pattern	Clifford Wolf	2014-08-14	1	-1/+11
*	Added module->ports	Clifford Wolf	2014-08-14	1	-0/+2
*	RIP $safe_pmux	Clifford Wolf	2014-08-14	1	-4/+2
*	Fixed SigBit(RTLIL::Wire *wire) constructor	Clifford Wolf	2014-08-12	1	-1/+1
*	Added support for truncating of wires to wreduce pass	Clifford Wolf	2014-08-05	1	-0/+7
*	Added RTLIL::IdString::in(...)	Clifford Wolf	2014-08-04	1	-5/+18