| Commit message (Collapse) | Author | Age | Files | Lines | ||
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| * | Fixed build with clang | Clifford Wolf | 2013-06-18 | 1 | -41/+69 | |
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| * | Added RTLIL::Module::fixup_ports() API and RTLIL::*::rewrite_sigspecs() API | Clifford Wolf | 2013-06-18 | 1 | -0/+48 | |
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| * | Added "dump" command (part ilang backend) | Clifford Wolf | 2013-06-02 | 1 | -9/+9 | |
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| * | Improved opt_share for reduce cells | Clifford Wolf | 2013-03-29 | 1 | -0/+2 | |
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| * | Added design->select() api and use it in extract pass | Clifford Wolf | 2013-03-03 | 1 | -0/+7 | |
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| * | Added id2cstr API | Clifford Wolf | 2013-03-01 | 1 | -0/+7 | |
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| * | Do not unescape identifiers starting with \$ | Clifford Wolf | 2013-03-01 | 1 | -1/+1 | |
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| * | initial import | Clifford Wolf | 2013-01-05 | 1 | -0/+341 | |
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index : iCE40/yosys | |
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