aboutsummaryrefslogtreecommitdiffstats
path: root/passes/memory/memory_map.cc
Commit message (Collapse)AuthorAgeFilesLines
* memory_map: Add -formal optionJannis Harder2022-08-161-17/+67
| | | | | | This maps memories for a global clock based formal verification flow. This implies -keepdc, uses $ff cells for ROMs and sets hdlname attributes.
* memory_map: avoid undriven unused FF inputs for -keepdcJannis Harder2022-06-281-0/+3
|
* memory_map: -keepdc option for formalJannis Harder2022-06-271-3/+14
| | | | Use it when invoking memory_map -rom-only from write_{smt2,btor}.
* memory_map: Add -rom-only option.Marcelina Kościelnicka2022-06-171-4/+18
|
* memory_map: Use const drivers instead of FFs for ROMs.Marcelina Kościelnicka2022-06-171-52/+59
|
* Fixing old e-mail addresses and deadnamesClaire Xenia Wolf2021-06-081-1/+1
| | | | | | | | s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi; s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi; s/((David)\s+)+Shah\s+<(dave|david)@(symbioticeda.com|yosyshq.com|ds0.me)>/David Shah <dave@ds0.me>/gi; s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi; s,https?://www.clifford.at/yosys/,http://yosyshq.net/yosys/,g;
* memory_map: Improve start_offset handling.Marcelina Kościelnicka2021-05-311-35/+31
| | | | Fixes #2775.
* memory_map: Add wide port support.Marcelina Kościelnicka2021-05-251-16/+17
|
* extract_rdff: Add initvals parameter.Marcelina Kościelnicka2021-05-231-2/+4
| | | | | This is not used yet, but will be needed when read port reset/initial value support lands.
* memory_map: Use Mem helpers.Marcelina Kościelnicka2020-10-211-138/+81
|
* Use C++11 final/override keywords.whitequark2020-06-181-2/+2
|
* Merge pull request #1603 from whitequark/ice40-ram_stylewhitequark2020-04-101-6/+113
|\ | | | | ice40/ecp5: add support for both 1364.1 and Synplify/LSE RAM/ROM attributes
| * memory_map: add -attr option, to respect inference attributes.whitequark2020-04-031-6/+113
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Before this commit, memory_map (which is always a part of a synth script) would always pick up any $mem cell that was not processed by a preceding pass and lower it down to $dff/$mux cells. This is undesirable for two reasons: * If there is an explicit inference attribute set on a $mem cell, e.g. (* ram_block *), then it is arguably incorrect to map such a memory to $dff/$mux cells. * If memory_map tries to lower a memory that was intended to be mapped to a large BRAM, it often takes extraordinarily long time to finish, produces an extremely large log file, and outputs an unusable design. After this commit, properly invoked memory_map will not map any memory that has an explicit inference attribute specified, solving the first issue, and alleviating the second. The default behavior is not changed.
* | kernel: big fat patch to use more ID::*, otherwise ID(*)Eddie Hung2020-04-021-58/+58
| |
* | kernel: use more ID::*Eddie Hung2020-04-021-13/+13
|/
* Use State::S{0,1}Eddie Hung2019-08-061-1/+1
|
* Consistent use of 'override' for virtual methods in derived classes.Henner Zeller2018-07-201-2/+2
| | | | | | | | | o Not all derived methods were marked 'override', but it is a great feature of C++11 that we should make use of. o While at it: touched header files got a -*- c++ -*- for emacs to provide support for that language. o use YS_OVERRIDE for all override keywords (though we should probably use the plain keyword going forward now that C++11 is established)
* Added "yosys -D" featureClifford Wolf2016-04-211-1/+1
|
* Added read-enable to memory modelClifford Wolf2015-09-251-12/+21
|
* Fixed trailing whitespacesClifford Wolf2015-07-021-4/+4
|
* Avoid parameter values with size 0 ($mem cells)Clifford Wolf2015-04-051-1/+6
|
* Various fixes for memories with offsetsClifford Wolf2015-02-141-2/+9
|
* Added $meminit support to "memory" commandClifford Wolf2015-02-141-2/+9
|
* Renamed SIZE() to GetSize() because of name collision on Win32Clifford Wolf2014-10-101-5/+5
|
* namespace YosysClifford Wolf2014-09-271-0/+4
|
* Improved write address decoder generation memory_mapClifford Wolf2014-08-301-16/+28
|
* Using worker class in memory_mapClifford Wolf2014-08-301-226/+231
|
* More cleanups related to RTLIL::IdString usageClifford Wolf2014-08-021-2/+2
|
* Renamed port access function on RTLIL::Cell, added param access functionsClifford Wolf2014-07-311-35/+35
|
* Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespaceClifford Wolf2014-07-311-1/+1
|
* Using log_assert() instead of assert()Clifford Wolf2014-07-281-1/+0
|
* Refactoring: Renamed RTLIL::Design::modules to modules_Clifford Wolf2014-07-271-1/+1
|
* Refactoring: Renamed RTLIL::Module::cells to cells_Clifford Wolf2014-07-271-1/+1
|
* Refactoring: Renamed RTLIL::Module::wires to wires_Clifford Wolf2014-07-271-1/+1
|
* Changed a lot of code to the new RTLIL::Wire constructorsClifford Wolf2014-07-261-39/+14
|
* Changed users of cell->connections_ to the new API (sed command)Clifford Wolf2014-07-261-37/+37
| | | | | | | | | git grep -l 'connections_' | xargs sed -i -r -e ' s/(->|\.)connections_\["([^"]*)"\] = (.*);/\1set("\2", \3);/g; s/(->|\.)connections_\["([^"]*)"\]/\1get("\2")/g; s/(->|\.)connections_.at\("([^"]*)"\)/\1get("\2")/g; s/(->|\.)connections_.push_back/\1connect/g; s/(->|\.)connections_/\1connections()/g;'
* Renamed RTLIL::{Module,Cell}::connections to connections_Clifford Wolf2014-07-261-37/+37
|
* Use only module->addCell() and module->remove() to create and delete cellsClifford Wolf2014-07-251-33/+9
|
* SigSpec refactoring: using the accessor functions everywhereClifford Wolf2014-07-221-4/+4
|
* SigSpec refactoring: renamed chunks and width to __chunks and __widthClifford Wolf2014-07-221-4/+4
|
* Changes to "memory" pass for new $memwr/$mem WR_EN interfaceClifford Wolf2014-07-161-35/+53
|
* Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem)Clifford Wolf2014-02-031-34/+37
|
* Only generate write-enable $and if WE is not constant 1 in memory_mapClifford Wolf2014-02-021-15/+18
|
* Replaced RTLIL::Const::str with generic decoder methodClifford Wolf2013-12-041-1/+1
|
* Fixed bug in synthesis of memories that are never writtenClifford Wolf2013-10-171-2/+7
|
* Added help messages to memory_* passesClifford Wolf2013-03-011-4/+15
|
* initial importClifford Wolf2013-01-051-0/+334
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-04 15:39:07 +0000