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* opt_expr: Optimizations for `$bweqx` and `$bwmux`Jannis Harder2022-11-301-0/+63
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* opt_expr: Fix shift/shiftx optimizationsJannis Harder2022-11-301-3/+3
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* opt_expr: Constant fold mux, pmux, bmux, demux, eqx, nex cellsJannis Harder2022-11-291-0/+33
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* opt_expr: Optimize bitwise logic ops with one fully const inputJannis Harder2022-11-291-0/+81
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* Consistent $mux undef handlingJannis Harder2022-10-241-1/+1
| | | | | | | | | | | | | | | | | | | * Change simlib's $mux cell to use the ternary operator as $_MUX_ already does * Stop opt_expr -keepdc from changing S=x to S=0 * Change const eval of $mux and $pmux to match the updated simlib (fixes sim) * The sat behavior of $mux already matches the updated simlib The verilog frontend uses $mux for the ternary operators and this changes all interpreations of the $mux cell (that I found) to match the verilog simulation behavior for the ternary operator. For 'if' and 'case' expressions the frontend may also use $mux but uses $eqx if the verilog simulation behavior is requested with the '-ifx' option. For $pmux there is a remaining mismatch between the sat behavior and the simlib behavior. Resolving this requires more discussion, as the $pmux cell does not directly correspond to a specific verilog construct.
* Hook up $aldff support in various passes.Marcelina Kościelnicka2021-10-021-2/+12
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* Add v2 memory cells.Marcelina Kościelnicka2021-08-111-1/+1
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* opt_expr: Propagate constants to port connections.Marcelina Kościelnicka2021-07-271-3/+22
| | | | | | | | This adds one simple piece of functionality to opt_expr: when a cell port is connected to a fully-constant signal (as determined by sigmap), the port is reconnected directly to the constant value. This is just enough optimization to fix the "non-constant $meminit input" problem without requiring a full opt_clean or a separate pass.
* opt_expr: Fix mul/div/mod by POT patterns to support >= 32 bits.Marcelina Kościelnicka2021-06-091-122/+85
| | | | | The previous code, in addition to being needlessly limitted to 32 bits in the first place, also had UB for the 31th bit (doing 1 << 31).
* opt_expr: Optimize div/mod by const 1.Marcelina Kościelnicka2021-06-091-4/+4
| | | | | | | | Turns out the code for div by a power of 2 is already almost capable of optimizing this to a shift-by-0 or and-with-0, which will be further folded into nothingness; let's beef it up to handle div by 1 as well. Fixes #2820.
* Fixing old e-mail addresses and deadnamesClaire Xenia Wolf2021-06-081-1/+1
| | | | | | | | s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi; s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi; s/((David)\s+)+Shah\s+<(dave|david)@(symbioticeda.com|yosyshq.com|ds0.me)>/David Shah <dave@ds0.me>/gi; s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi; s,https?://www.clifford.at/yosys/,http://yosyshq.net/yosys/,g;
* opt_expr: Remove -clkinv option, make it the default.Marcelina Kościelnicka2020-07-311-9/+9
| | | | | Adds -noclkinv option just in case the old behavior was actually useful to someone.
* opt_expr: Fix handling of $_XNOR_ cells with A = B.Marcelina Kościelnicka2020-07-291-1/+1
| | | | Fixes #2311.
* opt_expr: Fix crash on $mul optimization with more zeros removed than Y has.Marcelina Kościelnicka2020-07-051-0/+8
| | | | Fixes #2221.
* Merge pull request #2168 from whitequark/assert-unused-exprsclairexen2020-06-251-1/+1
|\ | | | | Use (and ignore) the expression provided to log_assert in NDEBUG builds
| * Remove YS_ATTRIBUTE(unused) where present just for log_assert()/log_debug().whitequark2020-06-191-1/+1
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* | Add support for new FF types in some opt passes.Marcelina Kościelnicka2020-06-231-3/+32
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* Use C++11 final/override keywords.whitequark2020-06-181-2/+2
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* Add flooring division operatorXiretza2020-05-281-6/+25
| | | | | | | | | | The $div and $mod cells use truncating division semantics (rounding towards 0), as defined by e.g. Verilog. Another rounding mode, flooring (rounding towards negative infinity), can be used in e.g. VHDL. The new $divfloor cell provides this flooring division. This commit also fixes the handling of $div in opt_expr, which was previously optimized as if it was $divfloor.
* Add flooring modulo operatorXiretza2020-05-281-5/+28
| | | | | | | | | | | The $div and $mod cells use truncating division semantics (rounding towards 0), as defined by e.g. Verilog. Another rounding mode, flooring (rounding towards negative infinity), can be used in e.g. VHDL. The new $modfloor cell provides this flooring modulo (also known as "remainder" in several languages, but this name is ambiguous). This commit also fixes the handling of $mod in opt_expr, which was previously optimized as if it was $modfloor.
* opt_expr: Sx to Sz; spotted by @XiretzaEddie Hung2020-05-141-1/+1
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* Merge pull request #1994 from YosysHQ/eddie/fix_bug1758Eddie Hung2020-05-141-25/+111
|\ | | | | opt_expr: improve single-bit $and/$or/$xor/$xnor cells; gate cells too
| * Fix whitespaceEddie Hung2020-05-141-1/+1
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| * opt_expr: consume_x to require/imply !keepdcEddie Hung2020-05-081-5/+6
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| * opt_expr: restore consume_x; use for coarse grained tooEddie Hung2020-05-081-6/+6
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| * opt_expr: const_xnor replacement to pad Y with 1'b1Eddie Hung2020-04-241-1/+2
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| * opt_expr: more fixes for $xor/$xnorEddie Hung2020-04-241-23/+47
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| * opt_expr: do not group by X, more fixesEddie Hung2020-04-231-18/+59
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| * opt_expr: improve single-bit $and/$or/$xor/$xnor cells; gate cells tooEddie Hung2020-04-231-10/+29
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* | Fix the other "opt_expr -fine" bug introduced in 213a89558Claire Wolf2020-05-021-7/+19
| | | | | | | | Signed-off-by: Claire Wolf <claire@symbioticeda.com>
* | Fix "opt_expr -fine" bug introduced in 213a89558Claire Wolf2020-05-011-7/+19
|/ | | | Signed-off-by: Claire Wolf <claire@symbioticeda.com>
* opt_expr: Fix X and CO outputs for $alu identity-mapping rules.Marcelina Kościelnicka2020-04-161-2/+17
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* opt_expr: Add more $alu optimizations.Marcelina Kościelnicka2020-04-141-19/+110
| | | | | | | | | | | Detect the places in the $alu where the carry bit is constant (due to const A[i] == B[i] ^ BI) and split it into smaller $alu at these points. Also, make the existing const-carry detection for low bits more generic (now handles cases where both BI and CI are constant, but not equal to one another). Fixes #1912.
* opt_expr: Optimize multiplications with low 0 bits in operands.Marcelina Kościelnicka2020-04-131-0/+33
| | | | Fixes #1500.
* kernel: big fat patch to use more ID::*, otherwise ID(*)Eddie Hung2020-04-021-147/+147
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* Merge pull request #1845 from YosysHQ/eddie/kernel_speedupEddie Hung2020-04-021-4/+4
|\ | | | | kernel: speedup by using more pass-by-const-ref
| * kernel: SigSpec use more const& + overloads to prevent implicit SigSpecEddie Hung2020-03-131-4/+4
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* | Merge pull request #1828 from YosysHQ/eddie/celltypes_speedupEddie Hung2020-04-011-3/+3
|\ \ | | | | | | kernel: share a single CellTypes within a pass
| * | Code review fixesEddie Hung2020-03-301-1/+1
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| * | kernel: share a single CellTypes within a passEddie Hung2020-03-181-3/+3
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* | Merge pull request #1790 from YosysHQ/eddie/opt_expr_xorEddie Hung2020-04-011-3/+37
|\ \ | | | | | | opt_expr: optimise $xor/$xnor/$_XOR_/$_XNOR_ -s with constant inputs
| * | opt_expr: fix failing $xnor testEddie Hung2020-03-201-2/+17
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| * | opt_expr: fix missing braceEddie Hung2020-03-201-2/+4
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| * | opt_expr: extend to $xnor and $_XNOR_Eddie Hung2020-03-191-8/+12
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| * | opt_expr: optimise 1-bit $xor or $_XOR_ with constant inputEddie Hung2020-03-191-1/+14
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* | opt_expr: remove redundantEddie Hung2020-03-191-3/+0
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* | opt_expr: optimise $sub when both A[i] and B[i] == 1'b1Eddie Hung2020-03-191-9/+20
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* | opt_expr: optimise for identity $alu-s just like $add/$subEddie Hung2020-03-191-7/+31
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* Fix opt_expr.eqneq.cmpzero debug printAlyssa Milburn2019-12-151-1/+1
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* Fix handling of z_digit "?" and fix optimization of cmp with "z"Clifford Wolf2019-09-131-0/+4
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
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