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* Fitting help messages to 80 character widthKrystalDelusion2022-08-241-3/+3
* Update commentScott Thibault2022-02-021-1/+1
* Fix unextend method for signed constantsScott Thibault2022-02-021-2/+1
* Make it work on allMiodrag Milanovic2021-11-051-2/+4
* Correct way of setting maybe_unsused on labelsMiodrag Milanovic2021-11-051-4/+2
* Fixing old e-mail addresses and deadnamesClaire Xenia Wolf2021-06-087-7/+7
* Add _pm.h files to GENLIST, fixes vcxsrc targetMiodrag Milanovic2021-03-111-0/+9
* passes/pmgen/pmgen.py: trivial change to remove C++ compiler warningsLarry Doolittle2020-12-231-2/+2
* Return nice error in pmgen generated code, fixes #2482Miodrag Milanovic2020-12-091-2/+6
* Merge pull request #2333 from YosysHQ/mwk/peepopt-shiftmul-signedclairexen2020-08-201-5/+1
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| * peeopt.shiftmul: Add a signedness check.Marcelina Kościelnicka2020-08-051-5/+1
* | Merge pull request #2328 from YosysHQ/mwk/opt_dff-cleanupclairexen2020-08-203-175/+0
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| * | peepopt: Remove now-redundant dffmux pattern.Marcelina Kościelnicka2020-08-073-175/+0
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* / peepopt.muldiv: Add a signedness check.Marcelina Kościelnicka2020-08-041-1/+4
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* synth_ice40: Use opt_dff.Marcelina Kościelnicka2020-07-302-247/+86
* synth_xilinx: Use opt_dff.Marcelina Kościelnicka2020-07-305-861/+200
* Use [[maybe_unused]] instead of YS_ATTRIBUTE(unused).whitequark2020-06-191-10/+10
* Use C++11 final/override keywords.whitequark2020-06-186-12/+12
* xilinx: xilinx_dsp_cascade to check CREG for DSP48E1 onlyEddie Hung2020-04-221-1/+1
* Cleanup use of hard-coded default parameters in light of #1945Eddie Hung2020-04-227-48/+48
* kernel: big fat patch to use more ID::*, otherwise ID(*)Eddie Hung2020-04-026-178/+178
* kernel: use more ID::*Eddie Hung2020-04-021-2/+2
* Merge pull request #1657 from YosysHQ/dave/xilinx-dsp-multonlyDavid Shah2020-02-021-0/+7
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| * xilinx_dsp: Add multonly scratchpad var to bypassDavid Shah2020-02-011-0/+7
* | Fix $lut input ordering -- SigSpec(std::initializer_list<>) is backwardsEddie Hung2020-01-271-1/+1
* | ice40: reduce ABC9 internal fanout warnings with a param for CI->I3Eddie Hung2020-01-241-3/+12
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* xilinx_dsp: another typo; move xilinx specific testEddie Hung2020-01-171-1/+1
* ice40_dsp: fix typoEddie Hung2020-01-171-2/+2
* ConsistencyEddie Hung2020-01-172-4/+6
* xilinx_dsp: add parameter defaultsEddie Hung2020-01-171-7/+7
* ice40_dsp: add default values for parametersEddie Hung2020-01-172-11/+11
* ice40_dsp: tolerant of fanout-less outputs, as well as all-zero inputsEddie Hung2020-01-171-0/+5
* fixed invalid charMiodrag Milanovic2019-12-251-1/+1
* Minor nit fixesMarcin Kościelnicki2019-12-251-2/+2
* Fix OPMODE for PCIN->PCOUT cascades in xc6s, check B[01]REG tooEddie Hung2019-12-231-8/+18
* Fix CEA/CEB checkEddie Hung2019-12-231-2/+2
* Fix checking CE[AB] and for direct connectionsEddie Hung2019-12-231-18/+40
* Support unregistered cascades for A and B inputsEddie Hung2019-12-231-47/+74
* Add DSP48A* PCOUT -> PCIN cascade supportEddie Hung2019-12-231-10/+10
* xilinx_dsp: Initial DSP48A/DSP48A1 support.Marcin Kościelnicki2019-12-224-11/+886
* ice40_wrapcarry -unwrap to preserve 'src' attributeEddie Hung2019-12-091-1/+9
* -unwrap to create $lut not SB_LUT4 for opt_lutEddie Hung2019-12-091-7/+5
* Sensitive to direct inst of $__ICE40_CARRY_WRAPPER; recreate SB_LUT4Eddie Hung2019-12-091-7/+11
* ice40_wrapcarry to really preserve attributes via -unwrap optionEddie Hung2019-12-091-17/+55
* Drop keep=0 attributes on SB_CARRYEddie Hung2019-12-061-0/+8
* Merge SB_CARRY+SB_LUT4's attributes when creating $__ICE40_CARRY_WRAPPEREddie Hung2019-12-051-0/+1
* ice40_wrapcarry to preserve SB_CARRY's attributesEddie Hung2019-12-031-0/+2
* Check for either sign or zero extension for postAdd packingEddie Hung2019-11-261-3/+3
* Fix #1462, #1480.Marcin Kościelnicki2019-11-192-9/+11
* Makefile: don't assume python is called `python3`Sean Cross2019-10-191-2/+2
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