iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Merge branch 'eddie/fix_retime' into xc7srl	Eddie Hung	2019-04-05	2	-0/+34
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\| *	"&nf -D 0" fails => use "-D 1" instead	Eddie Hung	2019-04-05	1	-1/+1
\| *	abc -dff now implies "-D 0" otherwise retiming doesn't happen	Eddie Hung	2019-04-05	1	-0/+2
\| *	Added missing argument checking to "mutate" command	Clifford Wolf	2019-04-04	1	-0/+32
* \|	Merge branch 'map_cells_before_map_luts' into xc7srl	Eddie Hung	2019-04-04	1	-1/+1
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\| *	proc_mux: Fix crash when trying to optimize non-existant mux to shiftx	Sylvain Munaut	2019-04-03	1	-1/+1
* \|	Remove handling for $pmux, since #895	Eddie Hung	2019-04-03	1	-40/+0
* \|	Merge remote-tracking branch 'origin/master' into xc7srl	Eddie Hung	2019-04-03	6	-20/+130
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\| *	memory_bram: Consider read enable for address expansion register	David Shah	2019-04-02	1	-0/+2
\| *	Merge pull request #895 from YosysHQ/pmux2shiftx	Eddie Hung	2019-04-02	1	-0/+28
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\| \| *	Create one $shiftx per bit in width	Eddie Hung	2019-03-25	1	-10/+17
\| \| *	Add a pmux-to-shiftx optimisation to proc_mux	Eddie Hung	2019-03-23	1	-0/+21
\| * \|	Merge pull request #901 from trcwm/libertyfixes	Clifford Wolf	2019-03-28	1	-7/+54
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\| \| * \|	Liberty file parser now accepts superfluous ;	Niels Moseley	2019-03-27	1	-1/+1
\| \| * \|	Liberty file parser now accepts superfluous ;	Niels Moseley	2019-03-27	1	-7/+54
\| * \| \|	Merge pull request #903 from YosysHQ/bram_reset_transp	Clifford Wolf	2019-03-28	1	-0/+1
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\| \| * \|	memory_bram: Reset make_transp when growing read ports	David Shah	2019-03-27	1	-0/+1
\| * \| \|	Add "rename -output"	Clifford Wolf	2019-03-27	1	-3/+23
\| * \| \|	Improve "rename" help message	Clifford Wolf	2019-03-27	1	-0/+6
\| * \| \|	Add "cutpoint -undef"	Clifford Wolf	2019-03-26	1	-10/+14
\| * \| \|	Add "hdlname" attribute	Clifford Wolf	2019-03-26	1	-0/+2
* \| \| \|	Merge remote-tracking branch 'origin/master' into xc7srl	Eddie Hung	2019-03-25	6	-34/+339
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\| * \| \|	Add "cutpoint" pass	Clifford Wolf	2019-03-25	2	-0/+165
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\| * \|	Merge pull request #896 from YosysHQ/transp_fixes	Clifford Wolf	2019-03-25	1	-9/+16
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\| \| * \|	memory_bram: Fix multiclock make_transp	David Shah	2019-03-24	1	-9/+16
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\| * \|	spaces -> tabs	Niels Moseley	2019-03-25	1	-78/+78
\| * \|	EOL is now accepted as ';' replacement on lines that look like: feature_xyz(o...	Niels Moseley	2019-03-25	1	-4/+3
\| * \|	Updated the liberty parser to accept [A:B] ranges (AST has not been updated)....	Niels Moseley	2019-03-24	2	-7/+90
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\| *	Add "mutate -none -mode", "mutate -mode none"	Clifford Wolf	2019-03-23	1	-1/+30
\| *	Add "mutate -s <filename>"	Clifford Wolf	2019-03-23	1	-2/+24
* \|	Cope with SHREG not having E port; Revert $pmux fine tune	Eddie Hung	2019-03-23	1	-4/+3
* \|	Add support for SHREGMAP+$mux, also fine tune $pmux	Eddie Hung	2019-03-22	1	-1/+24
* \|	Leftover printf	Eddie Hung	2019-03-22	1	-1/+0
* \|	Fixes for multibit	Eddie Hung	2019-03-22	1	-18/+38
* \|	Working for 1 bit	Eddie Hung	2019-03-22	1	-11/+49
* \|	Merge remote-tracking branch 'origin/master' into xc7srl	Eddie Hung	2019-03-22	1	-1/+26
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\| *	Trim init attributes when resizing FFs in "wreduce", fixes #887	Clifford Wolf	2019-03-22	1	-1/+26
* \|	Opt	Eddie Hung	2019-03-21	1	-1/+1
* \|	Fix spacing	Eddie Hung	2019-03-20	1	-239/+239
* \|	Revert $__SHREG_ to orig; use $__XILINX_SHREG for variable length	Eddie Hung	2019-03-19	1	-5/+14
* \|	Add support for variable length Xilinx SRL > 128	Eddie Hung	2019-03-19	1	-6/+0
* \|	shregmap -tech xilinx to delete $shiftx for var length SRL	Eddie Hung	2019-03-19	1	-10/+3
* \|	Merge remote-tracking branch 'origin/master' into xc7srl	Eddie Hung	2019-03-19	4	-0/+1255
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\| *	Improve mix of src/wire/wirebit coverage in "mutate -list"	Clifford Wolf	2019-03-16	1	-29/+84
\| *	Add "fmcombine -fwd -bwd -nop"	Clifford Wolf	2019-03-15	1	-10/+59
\| *	Add fmcombine pass	Clifford Wolf	2019-03-15	2	-0/+293
\| *	Improvements in "mutate" list-reduce algorithm	Clifford Wolf	2019-03-15	1	-13/+36
\| *	Add "mutate -cfg", improve pick_cover behavior	Clifford Wolf	2019-03-14	1	-46/+101
\| *	Add a strictly coverage-driven mutation selection strategy	Clifford Wolf	2019-03-14	1	-1/+70
\| *	Improve "mutate" wire coverage metric	Clifford Wolf	2019-03-14	1	-1/+16