| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Rework xilinx_dsp postAdd for new wreduce call | Eddie Hung | 2019-09-25 | 1 | -3/+3 |
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| * | Fix memory issue since SigSpec& could be invalidated | Eddie Hung | 2019-09-25 | 1 | -6/+10 |
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| * | unextend only used in init | Eddie Hung | 2019-09-25 | 1 | -2/+1 |
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| * | Call 'wreduce' after mul2dsp to avoid unextend() | Eddie Hung | 2019-09-25 | 1 | -5/+4 |
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| * | "abc_padding" attr for blackbox outputs that were padded, remove them later | Eddie Hung | 2019-09-23 | 1 | -3/+16 |
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| * | Set [AB]CASCREG to legal values | Eddie Hung | 2019-09-23 | 1 | -6/+10 |
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| * | Comment to explain separating CREG packing | Eddie Hung | 2019-09-23 | 1 | -0/+8 |
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| * | Separate out CREG packing into new pattern, to avoid conflict with PREG | Eddie Hung | 2019-09-23 | 4 | -46/+273 |
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| * | Move log_debug("\n") later | Eddie Hung | 2019-09-23 | 1 | -1/+1 |
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| * | Move unextend initialisation later | Eddie Hung | 2019-09-23 | 1 | -12/+9 |
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| * | Use new port() overload once more | Eddie Hung | 2019-09-23 | 1 | -2/+2 |
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| * | Merge remote-tracking branch 'origin/master' into xc7dsp | Eddie Hung | 2019-09-23 | 1 | -1/+7 |
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| | * | Revert abc9.cc | Eddie Hung | 2019-09-20 | 1 | -1/+1 |
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| | * | Trim mismatched connection to be same (smallest) size | Eddie Hung | 2019-09-20 | 1 | -0/+6 |
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| | * | Fix first testcase in #1391 | Eddie Hung | 2019-09-20 | 2 | -2/+2 |
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| * | | Use new port/param overload in pmg | Eddie Hung | 2019-09-20 | 4 | -22/+22 |
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| * | | Output pattern matcher items as log_debug() | Eddie Hung | 2019-09-20 | 2 | -31/+27 |
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| * | | OPMODE is port not param | Eddie Hung | 2019-09-20 | 1 | -7/+6 |
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| * | | Merge remote-tracking branch 'origin/master' into xc7dsp | Eddie Hung | 2019-09-20 | 1 | -0/+18 |
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| | * | Add "add -mod" | Clifford Wolf | 2019-09-20 | 1 | -0/+18 |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | | Do not run xilinx_dsp_cascadeAB for now | Eddie Hung | 2019-09-20 | 1 | -1/+2 |
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| * | | WIP for xiinx_dsp_cascadeAB | Eddie Hung | 2019-09-20 | 1 | -3/+499 |
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| * | | Run until convergence | Eddie Hung | 2019-09-20 | 1 | -3/+9 |
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| * | | Cleanup ice40_dsp.pmg | Eddie Hung | 2019-09-20 | 1 | -12/+6 |
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| * | | Cleanup xilinx_dsp | Eddie Hung | 2019-09-20 | 1 | -1/+1 |
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| * | | More exceptions | Eddie Hung | 2019-09-20 | 1 | -2/+2 |
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| * | | Update doc | Eddie Hung | 2019-09-20 | 1 | -2/+2 |
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| * | | Add a xilinx_dsp_cascade matcher for PCIN -> PCOUT | Eddie Hung | 2019-09-20 | 4 | -54/+105 |
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| * | | Add an overload for port/param with default value | Eddie Hung | 2019-09-20 | 1 | -0/+8 |
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| * | | Small cleanup | Eddie Hung | 2019-09-20 | 1 | -19/+18 |
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| * | | Disable support for SB_MAC16 reset since it is async | Eddie Hung | 2019-09-19 | 2 | -3/+7 |
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| * | | SB_MAC16 ffCD to not pack same as ffO | Eddie Hung | 2019-09-19 | 1 | -2/+2 |
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| * | | Clarify | Eddie Hung | 2019-09-19 | 1 | -1/+2 |
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| * | | Update doc for ice40_dsp | Eddie Hung | 2019-09-19 | 1 | -1/+10 |
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| * | | Add an index | Eddie Hung | 2019-09-19 | 2 | -0/+3 |
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| * | | Fix width of D | Eddie Hung | 2019-09-19 | 1 | -1/+1 |
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| * | | Use ID() macro | Eddie Hung | 2019-09-19 | 2 | -210/+210 |
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| * | | Merge remote-tracking branch 'origin/clifford/fix1381' into xc7dsp | Eddie Hung | 2019-09-19 | 3 | -5/+173 |
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| | * | Add techmap_autopurge attribute, fixes #1381 | Clifford Wolf | 2019-09-19 | 1 | -5/+49 |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| | * | Added extractinv pass | Marcin Kościelnicki | 2019-09-19 | 2 | -0/+124 |
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| | * | Document (* gentb_skip *) attr for test_autotb | Eddie Hung | 2019-09-18 | 1 | -0/+3 |
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| * | | Re-enable sign extension for C input | Eddie Hung | 2019-09-19 | 1 | -4/+4 |
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| * | | Do not perform width-checks for DSP48E1 which is much more complicated | Eddie Hung | 2019-09-19 | 1 | -11/+0 |
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| * | | Remove TODO as check should not be necessary | Eddie Hung | 2019-09-19 | 1 | -1/+0 |
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| * | | Revert index to select | Eddie Hung | 2019-09-19 | 1 | -1/+1 |
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| * | | Cleanup xilinx_dsp too | Eddie Hung | 2019-09-19 | 1 | -37/+28 |
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| * | | Refactor ce{mux,pol} -> hold{mux,pol} | Eddie Hung | 2019-09-19 | 2 | -77/+77 |
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| * | | Add HOLD/RST support for SB_MAC16 | Eddie Hung | 2019-09-19 | 2 | -69/+116 |
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| * | | Add support for SB_MAC16 CD and H registers | Eddie Hung | 2019-09-19 | 2 | -13/+73 |
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| * | | Refactor ice40_dsp.pmg | Eddie Hung | 2019-09-19 | 2 | -194/+426 |
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index : iCE40/yosys | |
| clone of https://github.com/YosysHQ/yosys |
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