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| * | | | | | | | | Revert "Add TODO"Eddie Hung2019-08-071-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 6068a6bf0d91e3ab9a5eaa33894a816f1560f99a.
| * | | | | | | | | Add TODOEddie Hung2019-08-071-0/+2
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| * | | | | | | | | Compute box_lookup just onceEddie Hung2019-08-071-8/+24
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| * | | | | | | | Merge pull request #1213 from YosysHQ/eddie/wreduce_addClifford Wolf2019-08-072-3/+28
| |\ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | wreduce/opt_expr: improve width reduction for $add and $sub cells
| | * | | | | | | | Move LSB-trimming functionality from wreduce to opt_exprEddie Hung2019-08-062-23/+26
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| | * | | | | | | | Merge remote-tracking branch 'origin/master' into eddie/wreduce_addEddie Hung2019-08-067-43/+118
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| | * | | | | | | | Try and fix againEddie Hung2019-07-191-5/+4
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| | * | | | | | | Do not access beyond boundsEddie Hung2019-07-191-1/+1
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| | * | | | | | | Wrap A and B in sigmapEddie Hung2019-07-191-2/+2
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| | * | | | | | | Remove "top" from messageEddie Hung2019-07-191-1/+1
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| | * | | | | | Also optimise MSB of $subEddie Hung2019-07-191-3/+3
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| | * | | | | | wreduce for $subEddie Hung2019-07-191-0/+23
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| * | | | | | Tweak default gate costs, cleanup "stat -tech cmos"Clifford Wolf2019-08-071-16/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | | | | Redesign of cell cost APIClifford Wolf2019-08-071-22/+20
| | |/ / / / | |/| | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | | | Add $_NMUX_, add "abc -g cmos", add proper cmos cell costsClifford Wolf2019-08-063-29/+67
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | | | Merge pull request #1242 from jfng/fix-proc_prune-partialwhitequark2019-08-031-2/+11
| |\ \ \ \ \ | | | | | | | | | | | | | | proc_prune: Promote partially redundant assignments.
| | * | | | | proc_prune: Promote partially redundant assignments.Jean-François Nguyen2019-08-011-2/+11
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| * | | | | Merge pull request #1238 from mmicko/vsbuild_fixClifford Wolf2019-08-021-0/+1
| |\ \ \ \ \ | | | | | | | | | | | | | | Visual Studio build fix
| | * | | | | Visual Studio build fixMiodrag Milanovic2019-07-311-0/+1
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| * / / / / Fix formatting for msys2 mingw build using GetSizeMiodrag Milanovic2019-08-013-10/+10
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| * / / / Add "stat -tech cmos"Clifford Wolf2019-07-201-2/+29
| |/ / / | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | Merge pull request #1188 from YosysHQ/eddie/abc9_push_invertersEddie Hung2019-07-161-44/+127
| |\ \ \ | | | | | | | | | | abc9: push inverters driving box inputs (comb outputs) through $lut soft logic
| | * | | Add commentEddie Hung2019-07-131-0/+5
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| | * | | duplicate -> cloneEddie Hung2019-07-121-3/+3
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| | * | | More cleanupEddie Hung2019-07-121-8/+2
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| | * | | CleanupEddie Hung2019-07-121-29/+51
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| | * | | CleanupEddie Hung2019-07-121-10/+4
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| | * | | CleanupEddie Hung2019-07-121-15/+24
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| | * | | More cleanupEddie Hung2019-07-121-11/+10
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| | * | | CleanupEddie Hung2019-07-121-46/+16
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| | * | | CleanupEddie Hung2019-07-121-7/+1
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| | * | | CleanupEddie Hung2019-07-121-13/+109
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| * | | Merge pull request #1186 from YosysHQ/eddie/abc9_ice40_fixEddie Hung2019-07-161-2/+2
| |\ \ \ | | | | | | | | | | abc9/ice40: encapsulate SB_CARRY+SB_LUT4 into one box
| | * | | Do not double count cells in abcEddie Hung2019-07-121-2/+2
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| * | | Fix check logic in extract_faMiodrag Milanovic2019-07-161-2/+2
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| * | | Merge pull request #1189 from YosysHQ/eddie/fix1151Clifford Wolf2019-07-151-0/+4
| |\ \ \ | | | | | | | | | | Error out if enable > dbits in memory_bram file
| | * | | Error out if enable > dbitsEddie Hung2019-07-131-0/+4
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| * | | Merge pull request #1190 from YosysHQ/eddie/fix_1099Clifford Wolf2019-07-151-4/+8
| |\ \ \ | | | | | | | | | | extract_fa to return nothing more gracefully
| | * | | If ConstEval fails do not log_abort() but return gracefullyEddie Hung2019-07-131-4/+8
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| * / / opt_lut: make less chatty.whitequark2019-07-131-56/+38
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| * | Enable &mfs for abc9, even if it only currently works for ice40Eddie Hung2019-07-111-1/+1
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| * | Merge pull request #1179 from whitequark/attrmap-procClifford Wolf2019-07-111-0/+19
| |\ \ | | | | | | | | attrmap: also consider process, switch and case attributes
| | * | attrmap: also consider process, switch and case attributes.whitequark2019-07-101-0/+19
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* | | | Error out if abc9 not called with -lut or -lutsEddie Hung2019-07-111-0/+3
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* | | | Count $_NOT_ cells turned into $lutsEddie Hung2019-07-111-7/+2
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* | | | WIP for fixing partitioning, temporarily do not partitionEddie Hung2019-07-111-12/+34
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* | | | write_verilog with *.v extensionEddie Hung2019-07-101-1/+1
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* | | | Remove -retime from abc9, revert to abc behav with separate clock/en domainsEddie Hung2019-07-101-29/+61
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* | | | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-07-1011-57/+318
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| * | | Merge pull request #1177 from YosysHQ/clifford/asyncClifford Wolf2019-07-101-0/+7
| |\ \ \ | | |/ / | |/| | Fix clk2fflogic adff reset semantic to negative hold time on reset
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