iCE40/yosys - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
*	intel_alm: direct LUTRAM cell instantiation	Dan Ravensloft	2020-05-07	1	-29/+0
\| \| \| \| \| \| \| \| \| \|	By instantiating the LUTRAM cell directly, we avoid a trip through altsyncram, which speeds up Quartus synthesis time. This also gives a little more flexibility, as Yosys can build RAMs out of individual 32x1 LUTRAM cells. While working on this, I discovered that the mem_init0 parameter of <family>_mlab_cell gets ignored by Quartus.
*	synth_intel_alm: alternative synthesis for Intel FPGAs	Dan Ravensloft	2020-04-15	1	-0/+29
	By operating at a layer of abstraction over the rather clumsy Intel primitives, we can avoid special hacks like `dffinit -highlow` in favour of simple techmapping. This also makes the primitives much easier to manipulate, and more descriptive (no more cyclonev_lcell_comb to mean anything from a LUT2 to a LUT6).