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* Rename abc_* names/attributes to more precisely be abc9_*Eddie Hung2019-10-041-190/+0
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* Oops. Actually use __NAME__ in ABC_DSP48E1 macroEddie Hung2019-09-251-1/+1
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* GrammarEddie Hung2019-09-201-1/+1
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* Fix DSP48E1 timing by breaking P path if MREG or PREGEddie Hung2019-09-191-17/+32
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* Revert "Different approach to timing"Eddie Hung2019-09-191-63/+42
| | | | This reverts commit 41256f48a5f3231e231cbdf9380a26128f272044.
* Different approach to timingEddie Hung2019-09-191-42/+63
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* Add no MULT no DPORT configEddie Hung2019-09-131-96/+14
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* Add support for MULT and DPORTEddie Hung2019-09-131-1/+89
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* Refine diagramEddie Hung2019-09-131-12/+14
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* Add an ASCII drawingEddie Hung2019-09-121-3/+22
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* Finish explanationEddie Hung2019-09-121-4/+10
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* Initial DSP48E1 box supportEddie Hung2019-09-121-0/+108
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* xilinx to use abc_map.v with -max_iter 1Eddie Hung2019-08-201-58/+2
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* Remove sequential extensionEddie Hung2019-08-201-89/+0
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* Wrap SRL{16,32} tooEddie Hung2019-08-201-6/+26
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* Wrap LUTRAMs in order to capture comb/seq behaviourEddie Hung2019-08-201-0/+44
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* Remove mapping rulesEddie Hung2019-08-201-33/+0
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* Use abc_{map,unmap,model}.vEddie Hung2019-08-201-0/+148