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techlibs
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xilinx
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abc_xc7.box
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Author
Age
Files
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*
Fix $__XILINX_MUXF78 box timing
Eddie Hung
2019-07-01
1
-1
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+1
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*
Revert "Fix broken MUXFx box, use MUXF7x2 box instead"
Eddie Hung
2019-07-01
1
-5
/
+4
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This reverts commit a9a140aa6c84e71edc1a244cfe363400c7e09d90.
*
Fix broken MUXFx box, use MUXF7x2 box instead
Eddie Hung
2019-07-01
1
-4
/
+5
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*
MUXF78 -> $__MUXF78 to indicate internal
Eddie Hung
2019-06-26
1
-1
/
+1
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*
Merge remote-tracking branch 'origin/xaig' into xc7mux
Eddie Hung
2019-06-26
1
-2
/
+3
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\
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*
Update comment on boxes
Eddie Hung
2019-06-26
1
-2
/
+3
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*
Realistic delays for RAM32X1D too
Eddie Hung
2019-06-25
1
-2
/
+2
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*
Add RAM32X1D box info
Eddie Hung
2019-06-25
1
-2
/
+9
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*
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Cleanup abc_box_id
Eddie Hung
2019-06-26
1
-5
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+5
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*
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Realistic delays for RAM32X1D too
Eddie Hung
2019-06-24
1
-2
/
+2
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*
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Merge remote-tracking branch 'origin/xaig' into xc7mux
Eddie Hung
2019-06-24
1
-4
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+4
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\
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*
Use LUT delays for dist RAM delays
Eddie Hung
2019-06-24
1
-4
/
+4
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*
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Add RAM32X1D box info
Eddie Hung
2019-06-24
1
-2
/
+9
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*
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Merge remote-tracking branch 'origin/xaig' into xc7mux
Eddie Hung
2019-06-24
1
-0
/
+14
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\
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*
Add Xilinx dist RAM as comb boxes
Eddie Hung
2019-06-24
1
-0
/
+14
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*
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Merge remote-tracking branch 'origin/xaig' into xc7mux
Eddie Hung
2019-06-22
1
-46
/
+15
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\
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*
Add comment to xc7 box
Eddie Hung
2019-06-22
1
-0
/
+3
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*
Carry in/out box ordering now move to end, not swap with end
Eddie Hung
2019-06-22
1
-12
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+12
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*
Remove DFF and RAMD box info for now
Eddie Hung
2019-06-21
1
-34
/
+0
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*
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Add $__XILINX_MUXF78 to preserve entire box
Eddie Hung
2019-06-21
1
-3
/
+8
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/
*
As per @daveshah1 remove async DFF timing from xilinx
Eddie Hung
2019-06-14
1
-2
/
+2
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*
Rename +/xilinx/abc.{box,lut} -> abc_xc7.{box,lut}
Eddie Hung
2019-06-14
1
-0
/
+62
