| Commit message (Collapse) | Author | Age | Files | Lines | ||
|---|---|---|---|---|---|---|
| ... | ||||||
| * | | | | | Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dsp | Eddie Hung | 2019-08-30 | 1 | -24/+79 | |
| |\ \ \ \ \ | ||||||
| | * \ \ \ \ | Merge branch 'master' into xc7dsp | David Shah | 2019-08-30 | 1 | -24/+91 | |
| | |\ \ \ \ \ | | | |_|_|/ | | |/| | | | ||||||
| | | * | | | | Add (* clkbuf_sink *) to SRLC16E, reorder ports to match vendor | Eddie Hung | 2019-08-28 | 1 | -3/+8 | |
| | | | | | | | ||||||
| | | * | | | | xilinx: Add SRLC16E primitive. | Marcin Kościelnicki | 2019-08-27 | 1 | -1/+21 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | Fixes #1331. | |||||
| | | * | | | | Merge branch 'master' into mwk/xilinx_bufgmap | Eddie Hung | 2019-08-23 | 1 | -1/+1 | |
| | | |\ \ \ \ | | | | |_|/ | | | |/| | | ||||||
| | | | * | | | Forgot one | Eddie Hung | 2019-08-23 | 1 | -1/+2 | |
| | | | | | | | ||||||
| | | * | | | | Merge branch 'master' into mwk/xilinx_bufgmap | Eddie Hung | 2019-08-23 | 1 | -11/+22 | |
| | | |\| | | | ||||||
| | | | * | | | Put abc_* attributes above port | Eddie Hung | 2019-08-23 | 1 | -7/+14 | |
| | | | | |/ | | | |/| | ||||||
| | | * | | | Merge remote-tracking branch 'origin/master' into mwk/xilinx_bufgmap | Eddie Hung | 2019-08-23 | 1 | -14/+20 | |
| | | |\| | | ||||||
| | | * | | | move attributes to wires | Marcin Kościelnicki | 2019-08-13 | 1 | -33/+42 | |
| | | | | | | ||||||
| | | * | | | Add clock buffer insertion pass, improve iopadmap. | Marcin Kościelnicki | 2019-08-13 | 1 | -0/+16 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A few new attributes are defined for use in cell libraries: - iopad_external_pin: marks PAD cell's external-facing pin. Pad insertion will be skipped for ports that are already connected to such a pin. - clkbuf_sink: marks an input pin as a clock pin, requesting clock buffer insertion. - clkbuf_driver: marks an output pin as a clock buffer output pin. Clock buffer insertion will be skipped for nets that are already driven by such a pin. All three are module attributes that should be set to a comma-separeted list of pin names. Clock buffer insertion itself works as follows: 1. All cell ports, starting from bottom up, can be marked as clock sinks (requesting clock buffer insertion) or as clock buffer outputs. 2. If a wire in a given module is driven by a cell port that is a clock buffer output, it is in turn also considered a clock buffer output. 3. If an input port in a non-top module is connected to a clock sink in a contained cell, it is also in turn considered a clock sink. 4. If a wire in a module is driven by a non-clock-buffer cell, and is also connected to a clock sink port in a contained cell, a clock buffer is inserted in this module. 5. For the top module, a clock buffer is also inserted on input ports connected to clock sinks, optionally with a special kind of input PAD (such as IBUFG for Xilinx). 6. Clock buffer insertion on a given wire is skipped if the clkbuf_inhibit attribute is set on it. | |||||
| * | | | | | Merge remote-tracking branch 'origin/master' into xc7dsp | Eddie Hung | 2019-08-20 | 1 | -8/+20 | |
| |\ \ \ \ \ | | |_|/ / | |/| | | | ||||||
| | * | | | | Unify abc_carry_{in,out} into abc_carry and use port dir, as @mithro | Eddie Hung | 2019-08-19 | 1 | -2/+2 | |
| | | |_|/ | |/| | | ||||||
| | * | | | Attach abc_scc_break, abc_carry_{in,out} attr to ports not modules | Eddie Hung | 2019-08-16 | 1 | -8/+20 | |
| | | |/ | |/| | ||||||
| * | | | Add assign PCOUT = P to DSP48E1 | Eddie Hung | 2019-08-13 | 1 | -0/+2 | |
| | |/ |/| | ||||||
| * | | Fix copy-pasta typo | Eddie Hung | 2019-08-08 | 1 | -2/+2 | |
| | | | ||||||
| * | | DSP48E1 sim model: add SIMD tests | David Shah | 2019-08-08 | 1 | -1/+1 | |
| | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | |||||
| * | | DSP48E1 model: test CE inputs | David Shah | 2019-08-08 | 1 | -5/+8 | |
| | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | |||||
| * | | DSP48E1 sim model: seq test working | David Shah | 2019-08-08 | 1 | -6/+13 | |
| | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | |||||
| * | | DSP48E1 sim model: Comb, no pre-adder, mode working | David Shah | 2019-08-08 | 1 | -2/+3 | |
| | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | |||||
| * | | [wip] sim model testing | David Shah | 2019-08-08 | 1 | -2/+2 | |
| | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | |||||
| * | | [wip] sim model testing | David Shah | 2019-08-08 | 1 | -40/+49 | |
| | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | |||||
| * | | [wip] DSP48E1 sim model improvements | David Shah | 2019-08-07 | 1 | -6/+82 | |
| | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | |||||
| * | | [wip] DSP48E1 sim model improvements | David Shah | 2019-08-06 | 1 | -23/+120 | |
| | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | |||||
| * | | [wip] DSP48E1 sim model improvements | David Shah | 2019-08-06 | 1 | -8/+75 | |
| | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | |||||
| * | | Signedness | Eddie Hung | 2019-07-16 | 1 | -7/+7 | |
| | | | ||||||
| * | | Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dsp | Eddie Hung | 2019-07-16 | 1 | -1/+1 | |
| |\ \ | ||||||
| | * | | xilinx: Add correct signed behaviour to DSP48E1 model | David Shah | 2019-07-16 | 1 | -1/+1 | |
| | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | |||||
| * | | | Add support for {A,B,P}REG in DSP48E1 | Eddie Hung | 2019-07-16 | 1 | -5/+21 | |
| |/ / | ||||||
| * / | Move DSP48E1 model out of cells_xtra, initial multiply one in cells_sim | Eddie Hung | 2019-07-15 | 1 | -0/+131 | |
| |/ | ||||||
| * | xilinx: Fix the default values for FDPE/FDSE INIT attributes to match ↵ | Marcin Kościelnicki | 2019-07-11 | 1 | -2/+2 | |
| | | | | | ISE/Vivado. | |||||
| * | Revert "Fix broken MUXFx box, use MUXF7x2 box instead" | Eddie Hung | 2019-07-01 | 1 | -3/+3 | |
| | | | | | This reverts commit a9a140aa6c84e71edc1a244cfe363400c7e09d90. | |||||
| * | Fix broken MUXFx box, use MUXF7x2 box instead | Eddie Hung | 2019-07-01 | 1 | -3/+3 | |
| | | ||||||
| * | Fix CARRY4 abc_box_id | Eddie Hung | 2019-06-28 | 1 | -1/+1 | |
| | | ||||||
| * | Merge remote-tracking branch 'origin/master' into xc7mux | Eddie Hung | 2019-06-28 | 1 | -2/+2 | |
| |\ | ||||||
| | * | Refactor for one "abc_carry" attribute on module | Eddie Hung | 2019-06-27 | 1 | -2/+2 | |
| | | | ||||||
| | * | Merge origin/master | Eddie Hung | 2019-06-27 | 1 | -1/+1 | |
| | | | ||||||
| * | | Merge remote-tracking branch 'origin/xaig' into xc7mux | Eddie Hung | 2019-06-26 | 1 | -3/+3 | |
| |\| | ||||||
| | * | Add "WE" to dist RAM's abc_scc_break | Eddie Hung | 2019-06-26 | 1 | -3/+3 | |
| | | | ||||||
| | * | Add RAM32X1D box info | Eddie Hung | 2019-06-25 | 1 | -2/+3 | |
| | | | ||||||
| | * | Merge remote-tracking branch 'origin/master' into xaig | Eddie Hung | 2019-06-25 | 1 | -0/+17 | |
| | |\ | ||||||
| * | \ | Merge remote-tracking branch 'origin/eddie/fix1132' into xc7mux | Eddie Hung | 2019-06-26 | 1 | -1/+1 | |
| |\ \ \ | ||||||
| | * | | | Simulation model verilog fix | Miodrag Milanovic | 2019-06-26 | 1 | -1/+1 | |
| | | |/ | |/| | ||||||
| * | | | Cleanup abc_box_id | Eddie Hung | 2019-06-26 | 1 | -5/+5 | |
| | | | | ||||||
| * | | | Add RAM32X1D box info | Eddie Hung | 2019-06-24 | 1 | -2/+3 | |
| | | | | ||||||
| * | | | Merge remote-tracking branch 'origin/xaig' into xc7mux | Eddie Hung | 2019-06-24 | 1 | -0/+2 | |
| |\ \ \ | | |/ | |/| | ||||||
| | * | | Add Xilinx dist RAM as comb boxes | Eddie Hung | 2019-06-24 | 1 | -0/+2 | |
| | | | | ||||||
| * | | | Merge remote-tracking branch 'origin/eddie/ram32x1d' into xc7mux | Eddie Hung | 2019-06-24 | 1 | -0/+17 | |
| |\ \ \ | | |/ | |/| | ||||||
| | * | | Add RAM32X1D support | Eddie Hung | 2019-06-24 | 1 | -0/+17 | |
| | | | | ||||||
| * | | | Merge remote-tracking branch 'origin/xaig' into xc7mux | Eddie Hung | 2019-06-22 | 1 | -2/+0 | |
| |\ \ \ | | |/ | |/| | ||||||
 |
index : iCE40/yosys | |
| [no description] |
| aboutsummaryrefslogtreecommitdiffstats |