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techlibs
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xilinx
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cells_sim.v
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Merge remote-tracking branch 'origin/eddie/write_xaiger_improve' into xaig_dff
Eddie Hung
2019-11-27
1
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+28
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xilinx: Add simulation models for IOBUF and OBUFT.
Marcin Kościelnicki
2019-11-26
1
-0
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+28
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Merge remote-tracking branch 'origin/master' into xaig_dff
Eddie Hung
2019-11-25
1
-1
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+5
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clkbufmap: Add support for inverters in clock path.
Marcin Kościelnicki
2019-11-25
1
-1
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+5
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Merge remote-tracking branch 'origin/master' into xaig_dff
Eddie Hung
2019-11-19
1
-0
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+522
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xilinx: Add simulation models for MULT18X18* and DSP48A*.
Marcin Kościelnicki
2019-11-19
1
-0
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+511
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xilinx: Add simulation model for IBUFG.
Marcin Kościelnicki
2019-10-10
1
-0
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+11
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Do not require changes to cells_sim.v; try and work out comb model
Eddie Hung
2019-10-05
1
-208
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+16
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Merge remote-tracking branch 'origin/eddie/abc_to_abc9' into xaig_dff
Eddie Hung
2019-10-04
1
-47
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+47
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Rename abc_* names/attributes to more precisely be abc9_*
Eddie Hung
2019-10-04
1
-19
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+19
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More fixes
Eddie Hung
2019-10-01
1
-16
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+16
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Escape Verilog identifiers for legality outside of Yosys
Eddie Hung
2019-10-01
1
-48
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+48
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Remove need for $currQ port connection
Eddie Hung
2019-09-30
1
-80
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+80
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Merge remote-tracking branch 'origin/master' into xaig_dff
Eddie Hung
2019-09-30
1
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+44
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Add LDCE/LDPE sim library, remove from *cells_xtra.{v,py}
Eddie Hung
2019-09-30
1
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+44
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Merge remote-tracking branch 'origin/master' into xaig_dff
Eddie Hung
2019-09-29
1
-0
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+463
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Merge remote-tracking branch 'origin/clifford/fix1381' into xc7dsp
Eddie Hung
2019-09-19
1
-8
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+44
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Mis-spell
Eddie Hung
2019-09-18
1
-10
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+25
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Add pattern detection support for DSP48E1 model, check against vendor
Eddie Hung
2019-09-18
1
-4
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+43
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Merge remote-tracking branch 'origin/master' into xc7dsp
Eddie Hung
2019-09-05
1
-26
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+70
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Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dsp
Eddie Hung
2019-08-30
1
-24
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+79
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Merge branch 'master' into xc7dsp
David Shah
2019-08-30
1
-24
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+91
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Merge remote-tracking branch 'origin/master' into xc7dsp
Eddie Hung
2019-08-20
1
-8
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+20
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Add assign PCOUT = P to DSP48E1
Eddie Hung
2019-08-13
1
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+2
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Fix copy-pasta typo
Eddie Hung
2019-08-08
1
-2
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+2
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DSP48E1 sim model: add SIMD tests
David Shah
2019-08-08
1
-1
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+1
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DSP48E1 model: test CE inputs
David Shah
2019-08-08
1
-5
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+8
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DSP48E1 sim model: seq test working
David Shah
2019-08-08
1
-6
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+13
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DSP48E1 sim model: Comb, no pre-adder, mode working
David Shah
2019-08-08
1
-2
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+3
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[wip] sim model testing
David Shah
2019-08-08
1
-2
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+2
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[wip] sim model testing
David Shah
2019-08-08
1
-40
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+49
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[wip] DSP48E1 sim model improvements
David Shah
2019-08-07
1
-6
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+82
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[wip] DSP48E1 sim model improvements
David Shah
2019-08-06
1
-23
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+120
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[wip] DSP48E1 sim model improvements
David Shah
2019-08-06
1
-8
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+75
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Signedness
Eddie Hung
2019-07-16
1
-7
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+7
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Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dsp
Eddie Hung
2019-07-16
1
-1
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+1
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xilinx: Add correct signed behaviour to DSP48E1 model
David Shah
2019-07-16
1
-1
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+1
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Add support for {A,B,P}REG in DSP48E1
Eddie Hung
2019-07-16
1
-5
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+21
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Move DSP48E1 model out of cells_xtra, initial multiply one in cells_sim
Eddie Hung
2019-07-15
1
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+131
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FDCE_1 does not have IS_CLR_INVERTED
Eddie Hung
2019-09-29
1
-1
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+1
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Big rework; flop info now mostly in cells_sim.v
Eddie Hung
2019-09-28
1
-47
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+247
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Use extractinv for synth_xilinx -ise
Marcin Kościelnicki
2019-09-19
1
-8
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+44
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Remove trailing space
Eddie Hung
2019-08-30
1
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+2
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Merge remote-tracking branch 'origin/master' into xaig_arrival
Eddie Hung
2019-08-28
1
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+78
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Add (* clkbuf_sink *) to SRLC16E, reorder ports to match vendor
Eddie Hung
2019-08-28
1
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+8
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xilinx: Add SRLC16E primitive.
Marcin Kościelnicki
2019-08-27
1
-1
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+21
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Merge branch 'master' into mwk/xilinx_bufgmap
Eddie Hung
2019-08-23
1
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+1
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Merge branch 'master' into mwk/xilinx_bufgmap
Eddie Hung
2019-08-23
1
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+22
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Merge remote-tracking branch 'origin/master' into mwk/xilinx_bufgmap
Eddie Hung
2019-08-23
1
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+20
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move attributes to wires
Marcin Kościelnicki
2019-08-13
1
-33
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+42
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