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* Merge remote-tracking branch 'origin/eddie/write_xaiger_improve' into xaig_dffEddie Hung2019-11-271-0/+28
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| * xilinx: Add simulation models for IOBUF and OBUFT.Marcin Kościelnicki2019-11-261-0/+28
* | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-11-251-1/+5
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| * clkbufmap: Add support for inverters in clock path.Marcin Kościelnicki2019-11-251-1/+5
* | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-11-191-0/+522
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| * xilinx: Add simulation models for MULT18X18* and DSP48A*.Marcin Kościelnicki2019-11-191-0/+511
| * xilinx: Add simulation model for IBUFG.Marcin Kościelnicki2019-10-101-0/+11
* | Do not require changes to cells_sim.v; try and work out comb modelEddie Hung2019-10-051-208/+16
* | Merge remote-tracking branch 'origin/eddie/abc_to_abc9' into xaig_dffEddie Hung2019-10-041-47/+47
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| * Rename abc_* names/attributes to more precisely be abc9_*Eddie Hung2019-10-041-19/+19
* | More fixesEddie Hung2019-10-011-16/+16
* | Escape Verilog identifiers for legality outside of YosysEddie Hung2019-10-011-48/+48
* | Remove need for $currQ port connectionEddie Hung2019-09-301-80/+80
* | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-09-301-0/+44
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| * Add LDCE/LDPE sim library, remove from *cells_xtra.{v,py}Eddie Hung2019-09-301-0/+44
* | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-09-291-0/+463
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| * Merge remote-tracking branch 'origin/clifford/fix1381' into xc7dspEddie Hung2019-09-191-8/+44
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| * | Mis-spellEddie Hung2019-09-181-10/+25
| * | Add pattern detection support for DSP48E1 model, check against vendorEddie Hung2019-09-181-4/+43
| * | Merge remote-tracking branch 'origin/master' into xc7dspEddie Hung2019-09-051-26/+70
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| * \ \ Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dspEddie Hung2019-08-301-24/+79
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| | * \ \ Merge branch 'master' into xc7dspDavid Shah2019-08-301-24/+91
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| * | \ \ \ Merge remote-tracking branch 'origin/master' into xc7dspEddie Hung2019-08-201-8/+20
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| * | | | | | Add assign PCOUT = P to DSP48E1Eddie Hung2019-08-131-0/+2
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| * | | | | Fix copy-pasta typoEddie Hung2019-08-081-2/+2
| * | | | | DSP48E1 sim model: add SIMD testsDavid Shah2019-08-081-1/+1
| * | | | | DSP48E1 model: test CE inputsDavid Shah2019-08-081-5/+8
| * | | | | DSP48E1 sim model: seq test workingDavid Shah2019-08-081-6/+13
| * | | | | DSP48E1 sim model: Comb, no pre-adder, mode workingDavid Shah2019-08-081-2/+3
| * | | | | [wip] sim model testingDavid Shah2019-08-081-2/+2
| * | | | | [wip] sim model testingDavid Shah2019-08-081-40/+49
| * | | | | [wip] DSP48E1 sim model improvementsDavid Shah2019-08-071-6/+82
| * | | | | [wip] DSP48E1 sim model improvementsDavid Shah2019-08-061-23/+120
| * | | | | [wip] DSP48E1 sim model improvementsDavid Shah2019-08-061-8/+75
| * | | | | SignednessEddie Hung2019-07-161-7/+7
| * | | | | Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dspEddie Hung2019-07-161-1/+1
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| | * | | | | xilinx: Add correct signed behaviour to DSP48E1 modelDavid Shah2019-07-161-1/+1
| * | | | | | Add support for {A,B,P}REG in DSP48E1Eddie Hung2019-07-161-5/+21
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| * | | | | Move DSP48E1 model out of cells_xtra, initial multiply one in cells_simEddie Hung2019-07-151-0/+131
* | | | | | FDCE_1 does not have IS_CLR_INVERTEDEddie Hung2019-09-291-1/+1
* | | | | | Big rework; flop info now mostly in cells_sim.vEddie Hung2019-09-281-47/+247
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* | | | | Use extractinv for synth_xilinx -iseMarcin Kościelnicki2019-09-191-8/+44
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* | | | Remove trailing spaceEddie Hung2019-08-301-2/+2
* | | | Merge remote-tracking branch 'origin/master' into xaig_arrivalEddie Hung2019-08-281-15/+78
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| * | | Add (* clkbuf_sink *) to SRLC16E, reorder ports to match vendorEddie Hung2019-08-281-3/+8
| * | | xilinx: Add SRLC16E primitive.Marcin Kościelnicki2019-08-271-1/+21
| * | | Merge branch 'master' into mwk/xilinx_bufgmapEddie Hung2019-08-231-1/+1
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| * \ \ \ Merge branch 'master' into mwk/xilinx_bufgmapEddie Hung2019-08-231-11/+22
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| * \ \ \ \ Merge remote-tracking branch 'origin/master' into mwk/xilinx_bufgmapEddie Hung2019-08-231-14/+20
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| * | | | | move attributes to wiresMarcin Kościelnicki2019-08-131-33/+42