| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | xilinx: Still map LUT7/LUT8 to Xilinx specific primitives. | Tim 'mithro' Ansell | 2018-10-08 | 1 | -3/+2 |
| | | | | | | Then if targeting vpr map all the Xilinx specific LUTs back into generic Yosys LUTs. | ||||
| * | Consistent use of 'override' for virtual methods in derived classes. | Henner Zeller | 2018-07-20 | 1 | -2/+2 |
| | | | | | | | | | | o Not all derived methods were marked 'override', but it is a great feature of C++11 that we should make use of. o While at it: touched header files got a -*- c++ -*- for emacs to provide support for that language. o use YS_OVERRIDE for all override keywords (though we should probably use the plain keyword going forward now that C++11 is established) | ||||
| * | Improving vpr output support. | Tim 'mithro' Ansell | 2018-04-18 | 1 | -3/+34 |
| | | | | | | | | * Support output BLIF for Xilinx architectures. * Support using .names in BLIF for Xilinx architectures. * Use the same `NO_LUT` define in both `synth_ice40` and `synth_xilinx`. | ||||
| * | Add Xilinx RAM64X1D and RAM128X1D simulation models | Clifford Wolf | 2018-03-07 | 1 | -2/+0 |
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| * | Added "yosys -D" feature | Clifford Wolf | 2016-04-21 | 1 | -1/+1 |
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| * | Added black box modules for all the 7-series design elements (as listed in ↵ | Clifford Wolf | 2016-03-19 | 1 | -0/+2 |
| | | | | | ug953) | ||||
| * | Run dffsr2dff in synth_xilinx | Clifford Wolf | 2016-02-13 | 1 | -0/+2 |
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| * | Added "abc -luts" option, Improved Xilinx logic mapping | Clifford Wolf | 2016-02-01 | 1 | -2/+2 |
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| * | Bugfix in Xilinx LUT mapping | Clifford Wolf | 2015-10-30 | 1 | -1/+1 |
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| * | Added read-enable to memory model | Clifford Wolf | 2015-09-25 | 1 | -2/+2 |
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| * | Fixed trailing whitespaces | Clifford Wolf | 2015-07-02 | 1 | -3/+3 |
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| * | Added output args to synth_ice40 | Clifford Wolf | 2015-05-26 | 1 | -2/+2 |
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| * | Towards DRAM support in Xilinx flow | Clifford Wolf | 2015-04-09 | 1 | -0/+12 |
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| * | Added Xilinx bram black-box modules | Clifford Wolf | 2015-04-06 | 1 | -0/+2 |
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| * | Added "dffinit", Support for initialized Xilinx DFF | Clifford Wolf | 2015-04-04 | 1 | -5/+6 |
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| * | Added "stat" to "synth" and "synth_xilinx" | Clifford Wolf | 2015-02-15 | 1 | -0/+2 |
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| * | Added final checks to "synth" and "synth_xilinx" | Clifford Wolf | 2015-02-15 | 1 | -0/+10 |
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| * | no support for 6-series xilinx devices | Clifford Wolf | 2015-02-01 | 1 | -1/+1 |
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| * | Added Xilinx example for Basys3 board | Clifford Wolf | 2015-02-01 | 1 | -0/+2 |
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| * | Various cleanups in xilinx techlib | Clifford Wolf | 2015-01-18 | 1 | -6/+6 |
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| * | Added synth_xilinx -retime -flatten | Clifford Wolf | 2015-01-17 | 1 | -2/+28 |
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| * | Added MUXCY and XORCY support to synth_xilinx | Clifford Wolf | 2015-01-17 | 1 | -2/+10 |
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| * | Added dff2dffe to synth_xilinx | Clifford Wolf | 2015-01-16 | 1 | -0/+2 |
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| * | Added Xilinx MUXF7 and MUXF8 support | Clifford Wolf | 2015-01-15 | 1 | -2/+2 |
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| * | Various cleanups in synth_xilinx command | Clifford Wolf | 2015-01-13 | 1 | -54/+8 |
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| * | Various small improvements to synth_xilinx | Clifford Wolf | 2015-01-06 | 1 | -8/+6 |
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| * | Towards Xilinx bram support | Clifford Wolf | 2015-01-05 | 1 | -16/+20 |
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| * | namespace Yosys | Clifford Wolf | 2014-09-27 | 1 | -1/+5 |
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| * | Added "techmap -share_map" option | Clifford Wolf | 2013-11-24 | 1 | -4/+4 |
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| * | Added synth_xilinx command | Clifford Wolf | 2013-10-27 | 1 | -0/+210 |
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index : iCE40/yosys | |
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