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* Merge branch 'master' into xc7dspDavid Shah2019-08-301-13/+68
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| * Merge branch 'master' into mwk/xilinx_bufgmapEddie Hung2019-08-261-0/+8
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| | * Add undocumented featureEddie Hung2019-08-231-0/+8
| * | Merge remote-tracking branch 'origin/master' into mwk/xilinx_bufgmapEddie Hung2019-08-231-14/+17
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| | * Merge remote-tracking branch 'origin/master' into eddie/synth_xilinxEddie Hung2019-08-201-1/+1
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| | * | Work in progress for renaming labels/options in synth_xilinxEddie Hung2019-07-181-14/+17
| * | | minor review fixesMarcin Kościelnicki2019-08-131-1/+1
| * | | review fixesMarcin Kościelnicki2019-08-131-18/+27
| * | | Add clock buffer insertion pass, improve iopadmap.Marcin Kościelnicki2019-08-131-1/+36
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* | | xilinx: Rework labels for faster Verilator testingDavid Shah2019-08-131-1/+5
* | | Merge remote-tracking branch 'origin/master' into xc7dspEddie Hung2019-08-121-1/+1
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| * | stoi -> atoiEddie Hung2019-08-071-1/+1
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* | Pack partial-product adder DSP48E1 packingEddie Hung2019-08-091-0/+2
* | Combine techmap callsEddie Hung2019-08-081-2/+1
* | Move xilinx_dsp to before alumaccEddie Hung2019-08-081-6/+4
* | Change $__softmul back to $mulEddie Hung2019-08-011-0/+1
* | Use single DSP_SIGNEDONLY macroEddie Hung2019-07-181-1/+1
* | Update commentEddie Hung2019-07-171-5/+3
* | Revert drop down to 24x16 multipliers for allEddie Hung2019-07-161-1/+1
* | Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dspEddie Hung2019-07-161-1/+5
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| * | xilinx: Treat DSP48E1 as 24x17 unsigned for now (actual behaviour is 25x18 si...David Shah2019-07-161-1/+5
* | | Oops forgot these filesEddie Hung2019-07-151-0/+4
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* | Merge remote-tracking branch 'origin/master' into xc7dspEddie Hung2019-07-151-5/+20
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| * synth_xilinx: Initial Spartan 6 block RAM inference support.Marcin Kościelnicki2019-07-111-5/+20
* | Move dsp_map.v into cells_map.v; cleanup synth_xilinx a littleEddie Hung2019-07-101-4/+1
* | Merge remote-tracking branch 'origin/master' into xc7dspEddie Hung2019-07-101-43/+58
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| * Merge pull request #1180 from YosysHQ/eddie/no_abc9_retimeEddie Hung2019-07-101-5/+8
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| | * Error out if -abc9 and -retime specifiedEddie Hung2019-07-101-5/+8
| | * Remove peepopt call in synth_xilinx since already in synth -run coarseEddie Hung2019-06-281-5/+0
| * | Call muxpack and pmux2shiftx before cmp2lutEddie Hung2019-07-091-9/+12
| * | Restore opt_clean back to original placeEddie Hung2019-07-091-2/+1
| * | Restore missing techmap -map +/cmp2lut.v with LUT_WIDTH=6Eddie Hung2019-07-091-0/+2
| * | synth_xilinx to call commands of synth -coarse directlyEddie Hung2019-07-091-3/+20
| * | Revert "synth_xilinx to call "synth -run coarse" with "-keepdc""Eddie Hung2019-07-091-2/+2
| * | Fix spacingEddie Hung2019-07-091-1/+1
| * | Fix spacingEddie Hung2019-07-091-1/+1
| * | Do not call opt -mux_undef (part of -full) before muxcoverEddie Hung2019-07-081-1/+5
| * | synth_xilinx to call "synth -run coarse" with "-keepdc"Eddie Hung2019-07-081-2/+2
| * | CapitalisationEddie Hung2019-07-081-1/+1
| * | Add synth_xilinx -widemux recommended valueEddie Hung2019-07-081-1/+1
| * | Fixes for 2:1 muxesEddie Hung2019-07-081-1/+1
| * | synth_xilinx -widemux=2 is minimum nowEddie Hung2019-07-081-4/+7
| * | Parametric muxcover costs as per @daveshah1Eddie Hung2019-07-081-16/+14
| * | atoi -> stoi as per @daveshah1Eddie Hung2019-07-081-1/+1
* | | xc7: Map combinational DSP48E1sDavid Shah2019-07-081-5/+34
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* | Merge remote-tracking branch 'origin/master' into xc7muxEddie Hung2019-06-281-3/+0
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| * Remove redundant docEddie Hung2019-06-271-3/+0
* | Merge remote-tracking branch 'origin/xaig' into xc7muxEddie Hung2019-06-271-7/+10
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| * Add warning if synth_xilinx -abc9 with family != xc7Eddie Hung2019-06-271-0/+2
| * Merge origin/masterEddie Hung2019-06-271-7/+8
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