| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Fix unresolved conflict from #1573 | Eddie Hung | 2020-01-28 | 1 | -1/+1 |
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| * | Merge pull request #1573 from YosysHQ/eddie/xilinx_tristate | N. Engelhardt | 2020-01-28 | 1 | -0/+3 |
| |\ | | | | | synth_xilinx: error out if tristate without '-iopad' | ||||
| | * | Duplicate tribuf call, credit to @mwkmwkmwk | Eddie Hung | 2019-12-13 | 1 | -1/+0 |
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| | * | synth_xilinx: error out if tristate without '-iopad' | Eddie Hung | 2019-12-12 | 1 | -0/+4 |
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| * | | Deprecate `_CLB_CARRY from +/xilinx/arith_map.v since #1623 | Eddie Hung | 2020-01-17 | 1 | -2/+0 |
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| * | | Merge pull request #1636 from YosysHQ/eddie/fix_synth_xilinx_W | Miodrag Milanović | 2020-01-15 | 1 | -1/+1 |
| |\ \ | | | | | | | synth_xilinx: fix default W value for non-xc7 | ||||
| | * | | synth_xilinx: fix default W value for non-xc7 | Eddie Hung | 2020-01-14 | 1 | -1/+1 |
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| * | | | Merge pull request #1623 from YosysHQ/mmicko/edif_attr | Miodrag Milanović | 2020-01-14 | 1 | -1/+1 |
| |\ \ \ | |/ / |/| | | Export wire properties in EDIF | ||||
| | * | | Use CARRY4 for abc1 as well, preventing issues with Vivado | Miodrag Milanovic | 2020-01-10 | 1 | -1/+1 |
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| * | | | Another conflict | Eddie Hung | 2020-01-11 | 1 | -1/+0 |
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| * | | | synth_xilinx: synth_xilinx.abc9.xc7.W to replace XC7_WIRE_DELAY macro | Eddie Hung | 2020-01-10 | 1 | -4/+11 |
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| * | | synth_xilinx -dff to work with abc too | Eddie Hung | 2020-01-02 | 1 | -6/+14 |
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| * | | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2020-01-02 | 1 | -3/+3 |
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| | * \ | Merge pull request #1601 from YosysHQ/eddie/synth_retime | Eddie Hung | 2020-01-02 | 1 | -3/+3 |
| | |\ \ | | | | | | | | | "abc -dff" to no longer retime by default | ||||
| | | * | | Update doc that "-retime" calls abc with "-dff -D 1" | Eddie Hung | 2019-12-30 | 1 | -1/+1 |
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| | | * | | Revert "Revert "synth_* with -retime option now calls abc with -D 1 as well"" | Eddie Hung | 2019-12-30 | 1 | -2/+2 |
| | | | | | | | | | | | | | | | | | This reverts commit 6008bb7002f874e5c748eaa2050e7b6c17b32745. | ||||
| * | | | | abc9 -keepff -> -dff; refactor dff operations | Eddie Hung | 2020-01-02 | 1 | -3/+3 |
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| * | | | | Restore abc9 -keepff | Eddie Hung | 2020-01-01 | 1 | -1/+3 |
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| * | | | | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-12-30 | 1 | -12/+10 |
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| | * | | | Merge remote-tracking branch 'origin/master' into iopad_default | Miodrag Milanovic | 2019-12-28 | 1 | -1/+4 |
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| | | * | | xilinx_dsp: Initial DSP48A/DSP48A1 support. | Marcin Kościelnicki | 2019-12-22 | 1 | -1/+4 |
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| | * | | | Addressed review comments | Miodrag Milanovic | 2019-12-21 | 1 | -2/+3 |
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| | * | | | iopad no op for compatibility with old scripts | Miodrag Milanovic | 2019-12-21 | 1 | -0/+3 |
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| | * | | | Make iopad option default for all xilinx flows | Miodrag Milanovic | 2019-12-21 | 1 | -14/+5 |
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| | * | | Revert "Optimise write_xaiger" | Eddie Hung | 2019-12-20 | 1 | -5/+0 |
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| | * | | Merge pull request #1558 from YosysHQ/eddie/xaiger_cleanup | Eddie Hung | 2019-12-19 | 1 | -0/+5 |
| | |\ \ | | | | | | | | | Optimise write_xaiger | ||||
| | | * | | techmap/aigmap of whiteboxes to occur before abc9 instead of in write_xaiger | Eddie Hung | 2019-12-06 | 1 | -0/+5 |
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| * | | | Add "synth_xilinx -dff" option, cleanup abc9 | Eddie Hung | 2019-12-30 | 1 | -2/+14 |
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| * | | | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-12-19 | 1 | -4/+12 |
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| | * | | xilinx: Add xilinx_dffopt pass (#1557) | Marcin Kościelnicki | 2019-12-18 | 1 | -0/+1 |
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| | * | | xilinx: Improve flip-flop handling. | Marcin Kościelnicki | 2019-12-18 | 1 | -4/+11 |
| | |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds support for infering more kinds of flip-flops: - FFs with async set/reset and clock enable - FFs with sync set/reset - FFs with sync set/reset and clock enable Some passes have been moved (and some added) in order for dff2dffs to work correctly. This gives us complete coverage of Virtex 6+ and Spartan 6 flip-flop capabilities (though not latch capabilities). Older FPGAs also support having both a set and a reset input, which will be handled at a later data. | ||||
| * | | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-12-06 | 1 | -9/+8 |
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| | * | xilinx: Add tristate buffer mapping. (#1528) | Marcin Kościelnicki | 2019-12-04 | 1 | -9/+8 |
| | | | | | | | Fixes #1225. | ||||
| * | | Remove clkpart | Eddie Hung | 2019-12-05 | 1 | -4/+0 |
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| * | | techmap abc_unmap.v before xilinx_srl -fixed | Eddie Hung | 2019-12-03 | 1 | -6/+5 |
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| * | | clkpart -unpart into 'finalize' | Eddie Hung | 2019-11-28 | 1 | -3/+4 |
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| * | | ean call after abc{,9} | Eddie Hung | 2019-11-27 | 1 | -1/+2 |
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| * | | Move 'clean' from map_luts to finalize | Eddie Hung | 2019-11-26 | 1 | -1/+1 |
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| * | | For abc9, run clkpart before ff_map and after abc9 | Eddie Hung | 2019-11-23 | 1 | -0/+2 |
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| * | | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-11-19 | 1 | -30/+76 |
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| | * | synth_xilinx: Merge blackbox primitive libraries. | Marcin Kościelnicki | 2019-11-06 | 1 | -22/+3 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | First, there are no longer separate cell libraries for xc6s/xc7/xcu. Manually instantiating a primitive for a "wrong" family will result in yosys passing it straight through to the output, and it will be either upgraded or rejected by the P&R tool. Second, the blackbox library is expanded to cover many more families: everything from Spartan 3 up is included. Primitives for Virtex and Virtex 2 are listed in the Python file as well if we ever want to include them, but that would require having two different ISE versions (10.1 and 14.7) available when running cells_xtra.py, and so is probably more trouble than it's worth. Third, the blockram blackboxes are no longer in separate files — there is no practical reason to do so (from synthesis PoV, they are no different from any other cells_xtra blackbox), and they needlessly complicated the flow (among other things, merging them allows the user to use eg. Series 7 primitives and have them auto-upgraded to Ultrascale). Last, since xc5v logic synthesis appears to work reasonably well (the only major problem is lack of blockram inference support), xc5v is now an accepted setting for the -family option. | ||||
| | * | xilinx: Add URAM288 mapping for xcup | David Shah | 2019-10-23 | 1 | -1/+23 |
| | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
| | * | xilinx: Add support for UltraScale[+] BRAM mapping | David Shah | 2019-10-23 | 1 | -1/+6 |
| | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
| | * | xilinx: Support multiplier mapping for all families. | Marcin Kościelnicki | 2019-10-22 | 1 | -8/+45 |
| | | | | | | | | | | | This supports several older families that are not yet supported for actual logic synthesis — the intention is to add them soon. | ||||
| | * | Call memory_dff before DSP mapping to reserve registers (fixes #1447) | N. Engelhardt | 2019-10-17 | 1 | -0/+1 |
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| * | | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-10-08 | 1 | -5/+9 |
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| | * | Merge pull request #1437 from YosysHQ/eddie/abc_to_abc9 | Eddie Hung | 2019-10-08 | 1 | -7/+8 |
| | |\ | | | | | | | Rename abc_* names/attributes to more precisely be abc9_* | ||||
| | | * | Merge branch 'master' into eddie/abc_to_abc9 | Eddie Hung | 2019-10-04 | 1 | -3/+7 |
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| | * | | | Add comment on why partial multipliers are 18x18 | Eddie Hung | 2019-10-04 | 1 | -4/+8 |
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| | * | | | Fix typo in check_label() | Eddie Hung | 2019-10-04 | 1 | -1/+1 |
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index : iCE40/yosys | |
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