| Commit message (Collapse) | Author | Age | Files | Lines | ||
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| | * | | | | | | | | | Add init support | Eddie Hung | 2019-08-21 | 1 | -1/+1 | |
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| * | | | | | | | | | Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dsp | Eddie Hung | 2019-08-30 | 1 | -1/+52 | |
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| | * \ \ \ \ \ \ \ \ | Merge branch 'master' into xc7dsp | David Shah | 2019-08-30 | 1 | -13/+68 | |
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| | | * | | | | | | | | Merge branch 'master' into mwk/xilinx_bufgmap | Eddie Hung | 2019-08-26 | 1 | -0/+8 | |
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| | | | * | | | | | | | Add undocumented feature | Eddie Hung | 2019-08-23 | 1 | -0/+8 | |
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| | | * | | | | | | | Merge remote-tracking branch 'origin/master' into mwk/xilinx_bufgmap | Eddie Hung | 2019-08-23 | 1 | -14/+17 | |
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| | | * | | | | | | | minor review fixes | Marcin Kościelnicki | 2019-08-13 | 1 | -1/+1 | |
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| | | * | | | | | | | review fixes | Marcin Kościelnicki | 2019-08-13 | 1 | -18/+27 | |
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| | | * | | | | | | | Add clock buffer insertion pass, improve iopadmap. | Marcin Kościelnicki | 2019-08-13 | 1 | -1/+36 | |
| | | | |_|_|_|_|/ | | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A few new attributes are defined for use in cell libraries: - iopad_external_pin: marks PAD cell's external-facing pin. Pad insertion will be skipped for ports that are already connected to such a pin. - clkbuf_sink: marks an input pin as a clock pin, requesting clock buffer insertion. - clkbuf_driver: marks an output pin as a clock buffer output pin. Clock buffer insertion will be skipped for nets that are already driven by such a pin. All three are module attributes that should be set to a comma-separeted list of pin names. Clock buffer insertion itself works as follows: 1. All cell ports, starting from bottom up, can be marked as clock sinks (requesting clock buffer insertion) or as clock buffer outputs. 2. If a wire in a given module is driven by a cell port that is a clock buffer output, it is in turn also considered a clock buffer output. 3. If an input port in a non-top module is connected to a clock sink in a contained cell, it is also in turn considered a clock sink. 4. If a wire in a module is driven by a non-clock-buffer cell, and is also connected to a clock sink port in a contained cell, a clock buffer is inserted in this module. 5. For the top module, a clock buffer is also inserted on input ports connected to clock sinks, optionally with a special kind of input PAD (such as IBUFG for Xilinx). 6. Clock buffer insertion on a given wire is skipped if the clkbuf_inhibit attribute is set on it. | |||||
| * | | | | | | | | Merge remote-tracking branch 'origin/master' into xc7dsp | Eddie Hung | 2019-08-20 | 1 | -14/+17 | |
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| | * | | | | | | | Merge remote-tracking branch 'origin/master' into eddie/synth_xilinx | Eddie Hung | 2019-08-20 | 1 | -1/+1 | |
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| | * | | | | | | | Work in progress for renaming labels/options in synth_xilinx | Eddie Hung | 2019-07-18 | 1 | -14/+17 | |
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| * | | | | | | | | Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dsp | Eddie Hung | 2019-08-15 | 1 | -1/+5 | |
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| | * | | | | | | | xilinx: Rework labels for faster Verilator testing | David Shah | 2019-08-13 | 1 | -1/+5 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | |||||
| * | | | | | | | | Add DSP_A_MAXWIDTH_PARTIAL, refactor | Eddie Hung | 2019-08-13 | 1 | -1/+1 | |
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| * | | | | | | | Merge remote-tracking branch 'origin/master' into xc7dsp | Eddie Hung | 2019-08-12 | 1 | -1/+1 | |
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| | * | | | | | | stoi -> atoi | Eddie Hung | 2019-08-07 | 1 | -1/+1 | |
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| * | | | | | | Pack partial-product adder DSP48E1 packing | Eddie Hung | 2019-08-09 | 1 | -0/+2 | |
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| * | | | | | | Combine techmap calls | Eddie Hung | 2019-08-08 | 1 | -2/+1 | |
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| * | | | | | | Move xilinx_dsp to before alumacc | Eddie Hung | 2019-08-08 | 1 | -6/+4 | |
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| * | | | | | | Change $__softmul back to $mul | Eddie Hung | 2019-08-01 | 1 | -0/+1 | |
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| * | | | | | | Use single DSP_SIGNEDONLY macro | Eddie Hung | 2019-07-18 | 1 | -1/+1 | |
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| * | | | | | | Update comment | Eddie Hung | 2019-07-17 | 1 | -5/+3 | |
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| * | | | | | | Revert drop down to 24x16 multipliers for all | Eddie Hung | 2019-07-16 | 1 | -1/+1 | |
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| * | | | | | | Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dsp | Eddie Hung | 2019-07-16 | 1 | -1/+5 | |
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| | * | | | | | | xilinx: Treat DSP48E1 as 24x17 unsigned for now (actual behaviour is 25x18 ↵ | David Shah | 2019-07-16 | 1 | -1/+5 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | signed) Signed-off-by: David Shah <dave@ds0.me> | |||||
| * | | | | | | | Oops forgot these files | Eddie Hung | 2019-07-15 | 1 | -0/+4 | |
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| * | | | | | | Merge remote-tracking branch 'origin/master' into xc7dsp | Eddie Hung | 2019-07-15 | 1 | -5/+20 | |
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| | * | | | | | synth_xilinx: Initial Spartan 6 block RAM inference support. | Marcin Kościelnicki | 2019-07-11 | 1 | -5/+20 | |
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| * | | | | | Move dsp_map.v into cells_map.v; cleanup synth_xilinx a little | Eddie Hung | 2019-07-10 | 1 | -4/+1 | |
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| * | | | | | Merge remote-tracking branch 'origin/master' into xc7dsp | Eddie Hung | 2019-07-10 | 1 | -43/+58 | |
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| | * | | | | Merge pull request #1180 from YosysHQ/eddie/no_abc9_retime | Eddie Hung | 2019-07-10 | 1 | -5/+8 | |
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| | | * | | | | Error out if -abc9 and -retime specified | Eddie Hung | 2019-07-10 | 1 | -5/+8 | |
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| | | * | | | Remove peepopt call in synth_xilinx since already in synth -run coarse | Eddie Hung | 2019-06-28 | 1 | -5/+0 | |
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| | * | | | | Call muxpack and pmux2shiftx before cmp2lut | Eddie Hung | 2019-07-09 | 1 | -9/+12 | |
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| | * | | | | Restore opt_clean back to original place | Eddie Hung | 2019-07-09 | 1 | -2/+1 | |
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| | * | | | | Restore missing techmap -map +/cmp2lut.v with LUT_WIDTH=6 | Eddie Hung | 2019-07-09 | 1 | -0/+2 | |
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| | * | | | | synth_xilinx to call commands of synth -coarse directly | Eddie Hung | 2019-07-09 | 1 | -3/+20 | |
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| | * | | | | Revert "synth_xilinx to call "synth -run coarse" with "-keepdc"" | Eddie Hung | 2019-07-09 | 1 | -2/+2 | |
| | | | | | | | | | | | | | | | | | | | | | This reverts commit 7f964859ec99500e471853f5914b6e5b7c35a031. | |||||
| | * | | | | Fix spacing | Eddie Hung | 2019-07-09 | 1 | -1/+1 | |
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| | * | | | | Fix spacing | Eddie Hung | 2019-07-09 | 1 | -1/+1 | |
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| | * | | | | Do not call opt -mux_undef (part of -full) before muxcover | Eddie Hung | 2019-07-08 | 1 | -1/+5 | |
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| | * | | | | synth_xilinx to call "synth -run coarse" with "-keepdc" | Eddie Hung | 2019-07-08 | 1 | -2/+2 | |
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| | * | | | | Capitalisation | Eddie Hung | 2019-07-08 | 1 | -1/+1 | |
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| | * | | | | Add synth_xilinx -widemux recommended value | Eddie Hung | 2019-07-08 | 1 | -1/+1 | |
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| | * | | | | Fixes for 2:1 muxes | Eddie Hung | 2019-07-08 | 1 | -1/+1 | |
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| | * | | | | synth_xilinx -widemux=2 is minimum now | Eddie Hung | 2019-07-08 | 1 | -4/+7 | |
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| | * | | | | Parametric muxcover costs as per @daveshah1 | Eddie Hung | 2019-07-08 | 1 | -16/+14 | |
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| | * | | | | atoi -> stoi as per @daveshah1 | Eddie Hung | 2019-07-08 | 1 | -1/+1 | |
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| * | | | | | xc7: Map combinational DSP48E1s | David Shah | 2019-07-08 | 1 | -5/+34 | |
| |/ / / / | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | |||||
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index : iCE40/yosys | |
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