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* Fitting help messages to 80 character widthKrystalDelusion2022-08-241-3/+4
| | | | | | | | | Uses the regex below to search (using vscode): ^\t\tlog\("(.{10,}(?<!\\n)|.{81,}\\n)"\); Finds any log messages double indented (which help messages are) and checks if *either* there are is no newline character at the end, *or* the number of characters before the newline is more than 80.
* xilinx: Use `memory_libmap` pass.Marcelina Kościelnicka2022-05-181-43/+84
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* iopadmap: Add native support for negative-polarity output enable.Marcelina Kościelnicka2021-11-091-2/+3
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* Fixing old e-mail addresses and deadnamesClaire Xenia Wolf2021-06-081-1/+1
| | | | | | | | s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi; s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi; s/((David)\s+)+Shah\s+<(dave|david)@(symbioticeda.com|yosyshq.com|ds0.me)>/David Shah <dave@ds0.me>/gi; s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi; s,https?://www.clifford.at/yosys/,http://yosyshq.net/yosys/,g;
* Fix use of blif name in synth_xilinx commandMichael Christensen2021-04-271-1/+1
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* Blackbox all whiteboxes after synthesisgatecat2021-03-171-0/+1
| | | | | | | This prevents issues like processes in whiteboxes triggering an error in the JSON backend. Signed-off-by: gatecat <gatecat@ds0.me>
* Replace opt_rmdff with opt_dff.Marcelina Kościelnicka2020-08-071-3/+1
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* opt_expr: Remove -clkinv option, make it the default.Marcelina Kościelnicka2020-07-311-1/+1
| | | | | Adds -noclkinv option just in case the old behavior was actually useful to someone.
* synth_xilinx: Use opt_dff.Marcelina Kościelnicka2020-07-301-17/+12
| | | | | | | | | The main part is converting xilinx_dsp to recognize the new FF types created in opt_dff instead of trying to recognize the patterns on its own. The fsm call has been moved upwards because the passes cannot deal with $dffe/$sdff*, and other optimizations don't help it much anyway.
* Remove EXPLICIT_CARRY logic.Keith Rothman2020-07-231-14/+1
| | | | | | | The symbiflow-arch-defs tool chain no longer needs the EXPLICIT_CARRY within yosys itself. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* xilinx: Fix srl regression.Marcelina Kościelnicka2020-07-121-2/+2
| | | | | | | Of standard yosys cells, xilinx_srl only works on $_DFF_?_ and $_DFFE_?P_, which get upgraded to $_SDFFE_?P?P_ by dfflegalize at the point where xilinx_srl is called for non-abc9. Fix this by running ff_map.v first, resulting in FDRE cells, which are handled correctly.
* xilinx: Use dfflegalize.Marcelina Kościelnicka2020-07-091-11/+10
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* Update dff2dffe, dff2dffs, zinit to new FF types.Marcelina Kościelnicka2020-06-231-2/+2
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* Use C++11 final/override keywords.whitequark2020-06-181-5/+5
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* xilinx/ice40/ecp5: zinit requires selected wires, so select them allEddie Hung2020-05-141-2/+2
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* abc9_ops: add -prep_bypass for auto bypass boxes; refactorEddie Hung2020-05-141-3/+1
| | | | | Eliminate need for abc9_{,un}map.v in xilinx -prep_dff_{hier,unmap} -> -prep_hier
* synth_*: no need to explicitly read +/abc9_model.vEddie Hung2020-05-141-1/+1
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* synth_xilinx: rename dff_mode -> dffEddie Hung2020-05-141-8/+10
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* abc9_ops: add 'dff' label for auto handling of (* abc9_flop *) boxesEddie Hung2020-05-141-4/+1
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* synth_ice40/ecp5/xilinx: allow abc9.W to be overridden via scratchpadEddie Hung2020-05-041-3/+5
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* Get rid of dffsr2dff.Marcelina Kościelnicka2020-04-151-2/+1
| | | | | | This pass is a proper subset of opt_rmdff, which is called by opt, which is called by every synth flow in the coarse part. Thus, it never actually does anything and can be safely removed.
* synth_xilinx: techmap +/cmp2lut.v and +/cmp2lcu.v in 'coarse'Eddie Hung2020-04-031-2/+1
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* Update xilinx for ABC9Eddie Hung2020-02-271-1/+1
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* xilinx: improve specify functionalityEddie Hung2020-02-271-2/+2
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* Auto-generate .box/.lut files from specify blocksEddie Hung2020-02-271-1/+1
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* abc9_ops: -prep_box, to be called onceEddie Hung2020-02-271-1/+1
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* abc9_ops: -prep_lut and -write_lut to auto-generate LUT libraryEddie Hung2020-02-271-4/+2
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* Remove unnecessary commaEddie Hung2020-02-071-3/+2
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* xilinx: Add support for LUT RAM on LUT4-based devices.Marcin Kościelnicki2020-02-071-2/+1
| | | | | | | There are multiple other kinds of RAMs supported on these devices, but RAM16X1D is the only dual-port one. Fixes #1549
* xilinx: Initial support for LUT4 devices.Marcin Kościelnicki2020-02-071-16/+82
| | | | | | | Adds support for mapping logic, including LUTs, wide LUTs, and carry chains. Fixes #1547
* xilinx: Add block RAM mapping for Virtex 2* and Spartan 3*.Marcin Kościelnicki2020-02-071-1/+8
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* xilinx: Add support for Spartan 3A DSP block RAMs.Marcin Kościelnicki2020-02-071-1/+6
| | | | Part of #1550
* Add opt_lut_ins pass. (#1673)Marcelina Kościelnicka2020-02-031-0/+1
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* synth_xilinx: cleanup helpEddie Hung2020-01-281-6/+4
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* synth_xilinx: fix help when no active_design; fixes #1664Eddie Hung2020-01-281-2/+3
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* Fix unresolved conflict from #1573Eddie Hung2020-01-281-1/+1
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* Merge pull request #1573 from YosysHQ/eddie/xilinx_tristateN. Engelhardt2020-01-281-0/+3
|\ | | | | synth_xilinx: error out if tristate without '-iopad'
| * Duplicate tribuf call, credit to @mwkmwkmwkEddie Hung2019-12-131-1/+0
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| * synth_xilinx: error out if tristate without '-iopad'Eddie Hung2019-12-121-0/+4
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* | Deprecate `_CLB_CARRY from +/xilinx/arith_map.v since #1623Eddie Hung2020-01-171-2/+0
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* | Merge pull request #1636 from YosysHQ/eddie/fix_synth_xilinx_WMiodrag Milanović2020-01-151-1/+1
|\ \ | | | | | | synth_xilinx: fix default W value for non-xc7
| * | synth_xilinx: fix default W value for non-xc7Eddie Hung2020-01-141-1/+1
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* | | Merge pull request #1623 from YosysHQ/mmicko/edif_attrMiodrag Milanović2020-01-141-1/+1
|\ \ \ | |/ / |/| | Export wire properties in EDIF
| * | Use CARRY4 for abc1 as well, preventing issues with VivadoMiodrag Milanovic2020-01-101-1/+1
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* | | Another conflictEddie Hung2020-01-111-1/+0
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* | | synth_xilinx: synth_xilinx.abc9.xc7.W to replace XC7_WIRE_DELAY macroEddie Hung2020-01-101-4/+11
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* | synth_xilinx -dff to work with abc tooEddie Hung2020-01-021-6/+14
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* | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2020-01-021-3/+3
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| * \ Merge pull request #1601 from YosysHQ/eddie/synth_retimeEddie Hung2020-01-021-3/+3
| |\ \ | | | | | | | | "abc -dff" to no longer retime by default
| | * | Update doc that "-retime" calls abc with "-dff -D 1"Eddie Hung2019-12-301-1/+1
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