| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | xilinx: Test our DSP48A/DSP48A1 simulation models. | Marcin Kościelnicki | 2019-12-23 | 1 | -4/+7 |
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| * | Add pattern detection support for DSP48E1 model, check against vendor | Eddie Hung | 2019-09-18 | 1 | -3/+3 |
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| * | DSP48E1 sim model: add SIMD tests | David Shah | 2019-08-08 | 1 | -2/+4 |
| | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
| * | DSP48E1 sim model: fix seq tests and add preadder tests | David Shah | 2019-08-08 | 1 | -1/+2 |
| | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
| * | DSP48E1 sim model: seq test working | David Shah | 2019-08-08 | 1 | -1/+1 |
| | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
| * | [wip] sim model testing | David Shah | 2019-08-08 | 1 | -0/+11 |
| Signed-off-by: David Shah <dave@ds0.me> | |||||
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index : iCE40/yosys | |
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