| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | xilinx: Use `memory_libmap` pass. | Marcelina Kościelnicka | 2022-05-18 | 1 | -363/+0 |
| | | |||||
| * | Fixes xc7 BRAM36s | Maciej Dudek | 2021-07-30 | 1 | -4/+6 |
| | | | | | | | UG473 from Xilinx states that 15 bit should always be set if RAMB isn't in cascade mode. Signed-off-by: Maciej Dudek <mdudek@antmicro.com> | ||||
| * | xilinx: Add block RAM mapping for Virtex 2* and Spartan 3*. | Marcin Kościelnicki | 2020-02-07 | 1 | -0/+2 |
| | | |||||
| * | synth_xilinx: Initial Spartan 6 block RAM inference support. | Marcin Kościelnicki | 2019-07-11 | 1 | -0/+359 |
 |
index : iCE40/yosys | |
| [no description] |
| aboutsummaryrefslogtreecommitdiffstats |