| Commit message (Collapse) | Author | Age | Files | Lines | ||
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| | * | | | | | | | Use \$currQ | Eddie Hung | 2019-07-10 | 1 | -4/+9 | |
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| | * | | | | | | | Preserve all parameters, plus some extra ones for clk/en polarity | Eddie Hung | 2019-07-10 | 1 | -10/+66 | |
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| | * | | | | | | | Change how to specify flops to ABC again | Eddie Hung | 2019-07-10 | 1 | -13/+37 | |
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| | * | | | | | | | Remove params from FD*_1 variants | Eddie Hung | 2019-07-10 | 1 | -12/+3 | |
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| | * | | | | | | | Fix typo, and have !{PRE,CLR} behave as CE | Eddie Hung | 2019-07-10 | 1 | -14/+14 | |
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| | * | | | | | | | Move ABC FF stuff to abc_ff.v; add support for other FD* types | Eddie Hung | 2019-07-10 | 4 | -27/+135 | |
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| | * | | | | | | | Uncomment IS_C_INVERTED parameter | Eddie Hung | 2019-07-10 | 1 | -1/+1 | |
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| | * | | | | | | | synth_xilinx's map_cells stage to techmap ff_map.v | Eddie Hung | 2019-07-10 | 1 | -0/+2 | |
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| | * | | | | | | | Fix box numbering | Eddie Hung | 2019-07-10 | 2 | -5/+5 | |
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| | * | | | | | | | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-07-10 | 6 | -75/+446 | |
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| | * | | | | | | | | Capture all data in one "abc_flop" attribute | Eddie Hung | 2019-07-01 | 1 | -1/+1 | |
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| | * | | | | | | | | Update abc_box_id numbering | Eddie Hung | 2019-07-01 | 2 | -5/+5 | |
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| | * | | | | | | | | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-07-01 | 12 | -98/+228 | |
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| | * \ \ \ \ \ \ \ \ | Merge branch 'xaig' into xaig_dff | Eddie Hung | 2019-06-17 | 1 | -5/+5 | |
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| | * | | | | | | | | | | Add box delays for FD* | Eddie Hung | 2019-06-17 | 1 | -10/+10 | |
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| | * | | | | | | | | | | Merge remote-tracking branch 'origin/xaig' into xaig_dff | Eddie Hung | 2019-06-17 | 1 | -1/+2 | |
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| | * | | | | | | | | | | | Cleanup | Eddie Hung | 2019-06-16 | 3 | -11/+11 | |
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| | * | | | | | | | | | | | Add +/xilinx/abc_ff | Eddie Hung | 2019-06-15 | 1 | -0/+33 | |
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| | * | | | | | | | | | | | Fix spacing | Eddie Hung | 2019-06-15 | 1 | -1/+1 | |
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| | * | | | | | | | | | | | Use $__ABC_FF_ instead of $_FF_ | Eddie Hung | 2019-06-15 | 1 | -2/+10 | |
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| | * | | | | | | | | | | | Re-order alphabetically | Eddie Hung | 2019-06-15 | 1 | -1/+1 | |
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| | * | | | | | | | | | | | Fix initialisation of flops | Eddie Hung | 2019-06-15 | 2 | -12/+12 | |
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| | * | | | | | | | | | | | Map to $_FF_ instead of $_DFF_P_ to prevent recursion issues | Eddie Hung | 2019-06-15 | 2 | -2/+2 | |
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| | * | | | | | | | | | | | Wrap FDRE with $__ABC_FDRE containing comb | Eddie Hung | 2019-06-15 | 4 | -12/+29 | |
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| * | | | | | | | | | | | | Merge remote-tracking branch 'origin/master' into xc7dsp | Eddie Hung | 2019-08-30 | 1 | -14/+23 | |
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| | * \ \ \ \ \ \ \ \ \ \ \ | Merge remote-tracking branch 'origin/master' into eddie/xilinx_srl | Eddie Hung | 2019-08-30 | 1 | -3/+8 | |
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| | * | | | | | | | | | | | Merge remote-tracking branch 'origin/master' into eddie/xilinx_srl | Eddie Hung | 2019-08-28 | 7 | -194/+623 | |
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| | * \ \ \ \ \ \ \ \ \ \ \ | Merge branch 'master' into eddie/xilinx_srl | Eddie Hung | 2019-08-26 | 1 | -0/+8 | |
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| | * | | | | | | | | | | | | | xilinx_srl now copes with word-level flops $dff{,e} | Eddie Hung | 2019-08-23 | 1 | -8/+3 | |
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| | * | | | | | | | | | | | | | Merge remote-tracking branch 'origin/master' into eddie/xilinx_srl | Eddie Hung | 2019-08-23 | 1 | -8/+16 | |
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| | * | | | | | | | | | | | | | Add variable length support to xilinx_srl | Eddie Hung | 2019-08-21 | 1 | -4/+3 | |
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| | * | | | | | | | | | | | | | abc9 to perform new 'map_ffs' before 'map_luts' | Eddie Hung | 2019-08-21 | 1 | -3/+18 | |
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| | * | | | | | | | | | | | | | Add init support | Eddie Hung | 2019-08-21 | 1 | -1/+1 | |
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| * | | | | | | | | | | | | | Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dsp | Eddie Hung | 2019-08-30 | 7 | -204/+652 | |
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| | * \ \ \ \ \ \ \ \ \ \ \ \ | Merge branch 'master' into xc7dsp | David Shah | 2019-08-30 | 10 | -218/+682 | |
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| | | * | | | | | | | | | | | | Add (* clkbuf_sink *) to SRLC16E, reorder ports to match vendor | Eddie Hung | 2019-08-28 | 1 | -3/+8 | |
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| | | * | | | | | | | | | | | xilinx: Add SRLC16E primitive. | Marcin Kościelnicki | 2019-08-27 | 1 | -1/+21 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fixes #1331. | |||||
| | | * | | | | | | | | | | | Merge branch 'master' into mwk/xilinx_bufgmap | Eddie Hung | 2019-08-26 | 1 | -0/+8 | |
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| | | | * | | | | | | | | | | Add undocumented feature | Eddie Hung | 2019-08-23 | 1 | -0/+8 | |
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| | | * | | | | | | | | | | Merge branch 'master' into mwk/xilinx_bufgmap | Eddie Hung | 2019-08-23 | 1 | -1/+1 | |
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| | | | * | | | | | | | | | Forgot one | Eddie Hung | 2019-08-23 | 1 | -1/+2 | |
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| | | * | | | | | | | | | | Merge branch 'master' into mwk/xilinx_bufgmap | Eddie Hung | 2019-08-23 | 1 | -11/+22 | |
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| | | | * | | | | | | | | | Put abc_* attributes above port | Eddie Hung | 2019-08-23 | 1 | -7/+14 | |
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| | | * | | | | | | | | | Merge remote-tracking branch 'origin/master' into mwk/xilinx_bufgmap | Eddie Hung | 2019-08-23 | 5 | -30/+39 | |
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| | | * | | | | | | | | | move attributes to wires | Marcin Kościelnicki | 2019-08-13 | 6 | -283/+537 | |
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| | | * | | | | | | | | | minor review fixes | Marcin Kościelnicki | 2019-08-13 | 1 | -1/+1 | |
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| | | * | | | | | | | | | review fixes | Marcin Kościelnicki | 2019-08-13 | 1 | -18/+27 | |
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| | | * | | | | | | | | | Add clock buffer insertion pass, improve iopadmap. | Marcin Kościelnicki | 2019-08-13 | 6 | -71/+220 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A few new attributes are defined for use in cell libraries: - iopad_external_pin: marks PAD cell's external-facing pin. Pad insertion will be skipped for ports that are already connected to such a pin. - clkbuf_sink: marks an input pin as a clock pin, requesting clock buffer insertion. - clkbuf_driver: marks an output pin as a clock buffer output pin. Clock buffer insertion will be skipped for nets that are already driven by such a pin. All three are module attributes that should be set to a comma-separeted list of pin names. Clock buffer insertion itself works as follows: 1. All cell ports, starting from bottom up, can be marked as clock sinks (requesting clock buffer insertion) or as clock buffer outputs. 2. If a wire in a given module is driven by a cell port that is a clock buffer output, it is in turn also considered a clock buffer output. 3. If an input port in a non-top module is connected to a clock sink in a contained cell, it is also in turn considered a clock sink. 4. If a wire in a module is driven by a non-clock-buffer cell, and is also connected to a clock sink port in a contained cell, a clock buffer is inserted in this module. 5. For the top module, a clock buffer is also inserted on input ports connected to clock sinks, optionally with a special kind of input PAD (such as IBUFG for Xilinx). 6. Clock buffer insertion on a given wire is skipped if the clkbuf_inhibit attribute is set on it. | |||||
| * | | | | | | | | | | | Merge remote-tracking branch 'origin/master' into xc7dsp | Eddie Hung | 2019-08-20 | 5 | -24/+39 | |
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| | * | | | | | | | | | | Merge pull request #1209 from YosysHQ/eddie/synth_xilinx | Eddie Hung | 2019-08-20 | 4 | -16/+19 | |
| | |\ \ \ \ \ \ \ \ \ \ | | |_|_|_|_|_|_|_|_|/ | |/| | | | | | | | | | [WIP] synth xilinx renaming, as per #1184 | |||||
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index : iCE40/yosys | |
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