| Commit message (Collapse) | Author | Age | Files | Lines | |
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| * | Merge remote-tracking branch 'origin/master' into xc7dsp | Eddie Hung | 2019-08-30 | 1 | -14/+23 |
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| | * | Merge remote-tracking branch 'origin/master' into eddie/xilinx_srl | Eddie Hung | 2019-08-30 | 1 | -3/+8 |
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| | * \ | Merge remote-tracking branch 'origin/master' into eddie/xilinx_srl | Eddie Hung | 2019-08-28 | 7 | -194/+623 |
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| | * \ \ | Merge branch 'master' into eddie/xilinx_srl | Eddie Hung | 2019-08-26 | 1 | -0/+8 |
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| | * | | | | xilinx_srl now copes with word-level flops $dff{,e} | Eddie Hung | 2019-08-23 | 1 | -8/+3 |
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| | * | | | | Merge remote-tracking branch 'origin/master' into eddie/xilinx_srl | Eddie Hung | 2019-08-23 | 1 | -8/+16 |
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| | * | | | | | Add variable length support to xilinx_srl | Eddie Hung | 2019-08-21 | 1 | -4/+3 |
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| | * | | | | | abc9 to perform new 'map_ffs' before 'map_luts' | Eddie Hung | 2019-08-21 | 1 | -3/+18 |
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| | * | | | | | Add init support | Eddie Hung | 2019-08-21 | 1 | -1/+1 |
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| * | | | | | | Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dsp | Eddie Hung | 2019-08-30 | 7 | -204/+652 |
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| | * \ \ \ \ \ | Merge branch 'master' into xc7dsp | David Shah | 2019-08-30 | 10 | -218/+682 |
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| | | * | | | | | Add (* clkbuf_sink *) to SRLC16E, reorder ports to match vendor | Eddie Hung | 2019-08-28 | 1 | -3/+8 |
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| | | * | | | | xilinx: Add SRLC16E primitive. | Marcin Kościelnicki | 2019-08-27 | 1 | -1/+21 |
| | | | | | | | | | | | | | | | | | | | | | | | | | Fixes #1331. | ||||
| | | * | | | | Merge branch 'master' into mwk/xilinx_bufgmap | Eddie Hung | 2019-08-26 | 1 | -0/+8 |
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| | | | * | | | Add undocumented feature | Eddie Hung | 2019-08-23 | 1 | -0/+8 |
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| | | * | | | Merge branch 'master' into mwk/xilinx_bufgmap | Eddie Hung | 2019-08-23 | 1 | -1/+1 |
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| | | | * | | Forgot one | Eddie Hung | 2019-08-23 | 1 | -1/+2 |
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| | | * | | | Merge branch 'master' into mwk/xilinx_bufgmap | Eddie Hung | 2019-08-23 | 1 | -11/+22 |
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| | | | * | | Put abc_* attributes above port | Eddie Hung | 2019-08-23 | 1 | -7/+14 |
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| | | * | | Merge remote-tracking branch 'origin/master' into mwk/xilinx_bufgmap | Eddie Hung | 2019-08-23 | 5 | -30/+39 |
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| | | * | | move attributes to wires | Marcin Kościelnicki | 2019-08-13 | 6 | -283/+537 |
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| | | * | | minor review fixes | Marcin Kościelnicki | 2019-08-13 | 1 | -1/+1 |
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| | | * | | review fixes | Marcin Kościelnicki | 2019-08-13 | 1 | -18/+27 |
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| | | * | | Add clock buffer insertion pass, improve iopadmap. | Marcin Kościelnicki | 2019-08-13 | 6 | -71/+220 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A few new attributes are defined for use in cell libraries: - iopad_external_pin: marks PAD cell's external-facing pin. Pad insertion will be skipped for ports that are already connected to such a pin. - clkbuf_sink: marks an input pin as a clock pin, requesting clock buffer insertion. - clkbuf_driver: marks an output pin as a clock buffer output pin. Clock buffer insertion will be skipped for nets that are already driven by such a pin. All three are module attributes that should be set to a comma-separeted list of pin names. Clock buffer insertion itself works as follows: 1. All cell ports, starting from bottom up, can be marked as clock sinks (requesting clock buffer insertion) or as clock buffer outputs. 2. If a wire in a given module is driven by a cell port that is a clock buffer output, it is in turn also considered a clock buffer output. 3. If an input port in a non-top module is connected to a clock sink in a contained cell, it is also in turn considered a clock sink. 4. If a wire in a module is driven by a non-clock-buffer cell, and is also connected to a clock sink port in a contained cell, a clock buffer is inserted in this module. 5. For the top module, a clock buffer is also inserted on input ports connected to clock sinks, optionally with a special kind of input PAD (such as IBUFG for Xilinx). 6. Clock buffer insertion on a given wire is skipped if the clkbuf_inhibit attribute is set on it. | ||||
| * | | | | Merge remote-tracking branch 'origin/master' into xc7dsp | Eddie Hung | 2019-08-20 | 5 | -24/+39 |
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| | * | | | Merge pull request #1209 from YosysHQ/eddie/synth_xilinx | Eddie Hung | 2019-08-20 | 4 | -16/+19 |
| | |\ \ \ | | | | | | | | | | | [WIP] synth xilinx renaming, as per #1184 | ||||
| | | * \ \ | Merge remote-tracking branch 'origin/master' into eddie/synth_xilinx | Eddie Hung | 2019-08-20 | 3 | -6/+6 |
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| | | * | | | Update Makefile too | Eddie Hung | 2019-07-18 | 1 | -2/+2 |
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| | | * | | | Work in progress for renaming labels/options in synth_xilinx | Eddie Hung | 2019-07-18 | 3 | -14/+17 |
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| | * | | | | Unify abc_carry_{in,out} into abc_carry and use port dir, as @mithro | Eddie Hung | 2019-08-19 | 1 | -2/+2 |
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| | * | | | | Attach abc_scc_break, abc_carry_{in,out} attr to ports not modules | Eddie Hung | 2019-08-16 | 1 | -8/+20 |
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| * | | | | Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dsp | Eddie Hung | 2019-08-15 | 1 | -1/+5 |
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| | * | | | xilinx: Rework labels for faster Verilator testing | David Shah | 2019-08-13 | 1 | -1/+5 |
| | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
| * | | | | Add assign PCOUT = P to DSP48E1 | Eddie Hung | 2019-08-13 | 1 | -0/+2 |
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| * | | | | Add DSP_A_MAXWIDTH_PARTIAL, refactor | Eddie Hung | 2019-08-13 | 1 | -1/+1 |
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| * | | | Merge remote-tracking branch 'origin/master' into xc7dsp | Eddie Hung | 2019-08-12 | 1 | -1/+1 |
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| | * | | stoi -> atoi | Eddie Hung | 2019-08-07 | 1 | -1/+1 |
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| * | | | Pack partial-product adder DSP48E1 packing | Eddie Hung | 2019-08-09 | 1 | -0/+2 |
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| * | | | Remove signed from ports in +/xilinx/dsp_map.v | Eddie Hung | 2019-08-08 | 1 | -1/+1 |
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| * | | | Combine techmap calls | Eddie Hung | 2019-08-08 | 1 | -2/+1 |
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| * | | | Move xilinx_dsp to before alumacc | Eddie Hung | 2019-08-08 | 1 | -6/+4 |
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| * | | | INMODE is 5 bits | Eddie Hung | 2019-08-08 | 1 | -1/+1 |
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| * | | | Fix copy-pasta typo | Eddie Hung | 2019-08-08 | 1 | -2/+2 |
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| * | | | DSP48E1 sim model: add SIMD tests | David Shah | 2019-08-08 | 3 | -3/+113 |
| | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
| * | | | DSP48E1 model: test CE inputs | David Shah | 2019-08-08 | 2 | -7/+17 |
| | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
| * | | | DSP48E1 sim model: fix seq tests and add preadder tests | David Shah | 2019-08-08 | 2 | -6/+91 |
| | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
| * | | | DSP48E1 sim model: seq test working | David Shah | 2019-08-08 | 3 | -16/+60 |
| | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
| * | | | DSP48E1 sim model: Comb, no pre-adder, mode working | David Shah | 2019-08-08 | 2 | -8/+13 |
| | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
| * | | | [wip] sim model testing | David Shah | 2019-08-08 | 4 | -15/+77 |
| | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
| * | | | [wip] sim model testing | David Shah | 2019-08-08 | 3 | -40/+360 |
| | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
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index : iCE40/yosys | |
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